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Data/SFR - Data RAM and main SFR(Acc, B, PSW, SP, DPL, DPH) unit
(C) C.c 2011 // i8051 project - IFMO, Spb. Russia


General:
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BusA - address buss
BusB - data bus #1 (main)
BusC - data bus #2
Acc, B, SP, PSW, DPL, DPH + Ram (128 bytes)


Microcode map:
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Bit Description
0 Write data memory from BusB to Data[BusA]
1 Write Acc from BusB
2 ^ --- B
3 ^ --- SP
4 Inc SP
5 Dec SP
6 Write PSW from BusB
7 Inc DPTR
8 Write DPL from bus B
9 Write DPH from bus B
10-13 BusB8 source selection
0000 Null - use it if you don't need anything from this unit
0001 Wrk2
0010 Wrk1
0011 DPH
0100 DPL
0101 PSW
0110 Data[BusA]
0111 SP
1000 B
1001 Psw RLC (Psw that mus be after RLC operation)
1010 Psw RRC
1011 AccRLC
1100 AccRRC
1101 AccRR
1110 AccRL
1111 Acc
14 Write Wrk1 from Wrk1Src (see below)
15 ^ --- Wrk2
16 Select source for Wrk1 (0 - BusB, 1 - BusC)
17 ^ --- Wrk2
18-21 BusC source selection // unactual
0000 Null
0001 Wrk2
0010 Wrk1
.... Reserved/Null
1100 AccSwap
1101 Acc
1110 CRPsw
1111 CR (decimal addiction value (00/06/60/66h))
22-24 BusA source selection
000 Reserved/Null
001 Bit address
010 Psw Bank# + IR[2..0] (for Rj register support)
011 Psw Bank# + IR[0] (for Ri register support)
100 Acc
101 Wrk2
110 Wrk1
111 SP

MulDiv control (external block)
25 BusB = (Acc*B & 0xff); BusC = (Acc*B) >> 8;
26 BusB = Acc/B; BusC = Acc%B;
27 BusB = MulPsw(Acc, B);
28 BusB = DivPsw(Acc, B);

29 ReadPort
30-31 Reserved