курсовые работы / команды - rr, xch, subb и другие запускать на полной студии 08 (не экспресс) / MyProject3 / X51

#include "X51.h"

X51::X51()
:DPTR(0), PC(0), RA(0), RB(0), IR(0), WRK(0), WRK1(0), WRK2(0), step(0),
 byte1(0), byte2(0)
{
	Ram = new unsigned char[256];
	Data = Ram;
	Idata = Data;
	Reg = Data;
	Bit = Ram + 0x20;
	Stack = Ram + 0x30;
	SFR = Ram + 0x80;	
	for (int i = 0; i < 1024; i++)
	{
		Code[i]  = 0;
		Xdata[i] = 0;
	}
	for (int i = 0; i < 256; i++)
	{
		Ram[i] = 0;
		Rom[i] = 0;
	}
	SP = 7;

//RR A
	Rom[0x03] = copRr;
//ACALL a11
	Rom[0x11] = copAcall;
	Rom[0x31] = copAcall;
	Rom[0x51] = copAcall;
	Rom[0x71] = copAcall;	
	Rom[0x91] = copAcall;
	Rom[0xB1] = copAcall;
	Rom[0xD1] = copAcall;
	Rom[0xF1] = copAcall;
//LCALL a16 
	Rom[0x12] =copLcall;
//XRL ad, A
	Rom[0x62] = copXrl_ad_A;
//XRL ad, #d
	Rom[0x63] = copXrl_ad_d;
//SUBB A, #d
	Rom[0x94] = copSubb_A_d;
//SUBB A, @Ri
	Rom[0x96] = copSubb_A_aR;	
	Rom[0x97] = copSubb_A_aR;
//XCH A, ad
	Rom[0xC5] = copXch_ad;
//XCH A, Ri
	Rom[0xC8] = copXch_R;  
	Rom[0xC9] = copXch_R;
	Rom[0xCA] = copXch_R;
	Rom[0xCB] = copXch_R;
	Rom[0xCC] = copXch_R;
	Rom[0xCD] = copXch_R;
	Rom[0xCE] = copXch_R;
	Rom[0xCF] = copXch_R;
//SETB bit
	Rom[0xD2] = copSetb_bit;
//SETB C
	Rom[0xD3] = copSetb_C;
//MOV A, @Ri
	Rom[0xE6] = copMov_A_aR;
	Rom[0xE7] = copMov_A_aR;
}

X51::~X51()
{
	delete[] Ram;
}

unsigned char& X51::R(const unsigned int i)
{
	return Ram[i + 8*(PSW[3]+PSW[4]*2)];
}

bool X51::isP(unsigned char res)
{
	return 1 & (res + (res >> 1) + (res >> 2) + (res >> 3) + (res >> 4) + (res >> 5) + (res >> 6) + (res >> 7));
}


bool X51::isOV(unsigned char res)
{
	return ((RA ^ RB) >> 7) && ((RB ^ res) >> 7);
}

bool X51::isC()
{
	return RA < (RB + PSW[7]);
}

void X51::Reset()
{
	DPTR = 0;
	PC = 0;
	RA = 0;
	RB = 0;
	IR = 0;
	WRK = 0;
	WRK1 = 0;
	WRK2 = 0;
	byte1 = 0;
	byte2 = 0;
	step = 0;
	PSW = 0;
	for (int i = 0; i < 256; i++)
	{
		Ram[i] = 0;
	}
	SP = 7;
}

void X51::operator() ()
{
	switch(Rom[IR])
	{
	//rr A
	case copRr:  
		switch(step)
		{
			//0 { sra, step }
		case 0: A = (A >> 1) + ((A & 1) << 7); step++; break;	
			//1 { Acx = PC, BasB = Code, IR = BasB, step0 }
		case 1: IR = Code[PC++]; step = 0; break;				
		}
		break;	

	//acall a11 
	case copAcall:
		switch(step)
		{
			//0 { Acx = PC, BasB = Code, Wrk = BasB, incPC, incSP, step }
		case 0: WRK = Code[PC++]; SP++; step++; break;							
			//1 { BasA =SP, BasC = PCL, SFR = BasC, incSP, step }
		case 1: Stack[SP++] = PC; step++; break;								
			//2 { BasA =SP, BasC = PCH, SFR = BasC, step }
		case 2: Stack[SP] = PC >> 8; step++; break;								
			//3 { BasB = WRK, PCL = BasB, BasC = IrPc, PCH = BasC, step}
		case 3: PC = WRK + ((IR & 0xE0) << 3) + (PC & 0xF800); step++; break;	
			//4  { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 4: IR = Code[PC++]; step = 0; break;								
		}
		break;

	//lcall a16 
	case copLcall:
		switch(step)
		{
			//0 { Acx = PC, BasB = Code, Wrk = BasB, incPC, step }
		case 0: WRK = Code[PC++]; step++; break;			
			//1 { Acx = PC, BasB = Code, Wrk1 = BasB, incPC, incSP, step }
		case 1: WRK1 = Code[PC++]; SP++; step++; break;		
			//2 { BasA =SP, BasC = PCL, SFR = BasC, incSP, step }
		case 2: Stack[SP++] = PC; step++; break;			
			//3 { BasA =SP, BasC = PCH, SFR = BasC, step }
		case 3: Stack[SP] = PC >> 8; step++; break;			
			//4 { BasB = WRK, PCL = BasB, BasC = WRK1, PCH = BasC, step }
		case 4: PC = WRK + (WRK1 << 8); step++; break;		
			//5 { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 5: IR = Code[PC++]; step = 0; break;			
		}
		break;

	// xrl ad, A
	case copXrl_ad_A:  
		switch(step)
		{
			//0 { Acx = PC, BasB = Code, Wrk = BasB, incPC, step }
		case 0: WRK = Code[PC++]; step++; break;			
			//1 { BasA = Wrk, BasB = RAM, RA = BasB, BasC = ACC, RB = ACC, step }
		case 1: RA = Ram[WRK]; RB = A; step++; break;
			//2 { BasA = Wrk, XRL, BasC = F, RAM = BasC, wpsw , step }
		case 2: Ram[WRK] = RA ^ RB; PSW[7] = 0; PSW[2] = isP(Ram[WRK]); step++; break;
			//3 { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 3: IR = Code[PC++]; step = 0; break;
		}
		break;
	
	// xrl ad, #d
	case copXrl_ad_d:  
		switch(step)
		{
			//0 { Acx = PC, BasB = Code, Wrk = BasB, incPC, step }
		case 0: WRK = Code[PC++]; step++; break;
			//1 { BasA = Wrk, BasB = RAM, RA = BasB, step }  
		case 1: RA = Ram[WRK]; step++; break;
			//2 { Acx = PC, BasB = Code, Wrk1 = BasB, incPC, step }
		case 2: WRK1 = Code[PC++]; step++; break;
			//3 { BasC = Wrk1, RB = BasC, step }
		case 3: RB = WRK1; step++; break;
			//4 { BasA = Wrk, XRL, BasC = F, RAM = BasC, wpsw , step }
		case 4: Ram[WRK] = RA ^ RB; PSW[7] = 0; PSW[2] = isP(Ram[WRK]); step++; break;
			//5 { Acx = PC, BasB = Code, IR = BasB,PC++, step0 }
		case 5: IR = Code[PC++]; step = 0; break;
		}
		break;

	//subb A, #d
	case copSubb_A_d:	
		switch (step)
		{
			//0 { Acx = PC, BasB = Code, RA = BasB, BasC = ACC, RB = BasC, incPC, step }
		case 0: RA = Code[PC++]; RB = A; step++; break;
			//1 { SUBB, wpsw, step }
		case 1: A = RB - RA - PSW[7]; PSW[7] = isC(); PSW[2] = isOV(A); step++; break;
			//2 { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 2: IR = Code[PC++]; step = 0; break;
		}
		break;

	//subb A, @Ri
	case copSubb_A_aR:
		switch (step)
		{
			//0 { BasA = Rj, BasB = RAM, WRK = BasB, step }
		case 0: WRK = R(IR&1); step++; break;
			//1 { BasA = WRK, BasB = RAM, RA = BasB, BasC = ACC, RB = BasC, step }
		case 1: RB = A; RA = Ram[WRK]; step++; break;
			//2 { SUBB, wpsw, step }
		case 2: A = RB - RA - PSW[7]; PSW[7] = isC(); PSW[2] = isOV(A); step++; break;
			//3 { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 3: IR = Code[PC++]; step = 0; break;
		}
		break;

	//xch A, ad
	case copXch_ad:  
		switch(step)
		{
			//0 { Acx = PC, BasB = Code, Wrk = BasB, incPC, step }
		case 0: WRK = Code[PC++]; step++; break;
			//1 { BasA = WRK, BasB = RAM, WRK1 = BasB, step }
		case 1: WRK1 = Ram[WRK]; step++; break;
			//2 { BasA = WRK, BasC = ACC, RAM = BasC, step }
		case 2: Ram[WRK] = A; step++; break;
			//3 { BasC = WRK1, ACC = BasC, Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 3: A = WRK1; IR = Code[PC++]; step = 0; break;
		}
		break;
	
	//xch A, Ri
	case copXch_R:
		switch(step)
		{
			//0 { BasB = ACC, WRK = BasB, step }
		case 0: WRK = A; step++; break;
			//1 { BasA = Ri, BasB = RAM, WRK1 = BasB, step }
		case 1: WRK1 = R(IR&7); step++; break;
			//2 { BasC = WRK1, ACC = BasC, step } 
		case 2: A = WRK1; step++; break;
			//3 { BasC = WRK, BasA = Ri, RAM = BasC, step } 
		case 3: R(IR&7) = WRK; step++; break;
			//4 { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 4: IR = Code[PC++]; step = 0; break;
		}
		break;

	//setb bit
	case copSetb_bit:
		switch (step)
		{
			//0 { Acx = PC, BasB = Code, Wrk = BasB, incPC, step }
		case 0: WRK = Code[PC++]; step++; break;
			//1 { ifo = WRK[7], BasB = Wrk&F8, WRK1 =  BasB, step }
		case 1: if (WRK >> 7) WRK1 = WRK & 0xF8; step++; break;
			//2 { ifo = ~WRK[7], BasB = Wrk20, WRK1 = BasB, step }
		case 2: if (!(WRK >> 7)) WRK1 = 0x20 + (WRK >> 3); step++; break;
			//3 { BasA = WRK1, BasB = RAM, WRK2 = BasB, step }
		case 3: WRK2 = Ram[WRK1]; step++; break;
			//4 { Bita = WRK2, Bita = WRK, SETB, BasA = WRK1, BasC = Bita, RAM = BasC, step }
		case 4: Ram[WRK1] = WRK2 | (1 << (WRK & 7)); step++; break;
			//5 { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 5: IR = Code[PC++]; step = 0; break;
		}
		break;

	//setb C
	case copSetb_C:
		switch (step)
		{
			//0 { C, step }
		case 0: PSW[7] = 1; step++; break;
			//1 { Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 1: IR = Code[PC++]; step = 0; break;
		}
		break;

	//mov A, @Ri
	case copMov_A_aR:
		switch(step)
		{
			//0 { BasA = Rj, BasB = RAM, WRK = BasB, step }
		case 0: WRK = R(IR&1); step++; break;
			//1 { BasA = WRK, BasB = RAM, WRK1 = BasB, step }
		case 1: WRK1 = Ram[WRK]; step++; break;
			//2 { BasC = WRK1, A = BaseC, Acx = PC, BasB = Code, IR = BasB, PC++, step0 }
		case 2: A = WRK1; IR = Code[PC++]; step = 0; break;
		}
		break;
	}
}