- •Features
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •D-/SDATA
- •UGND
- •UVCC
- •UCAP
- •RESET/PC1/dW
- •XTAL1
- •XTAL2/PC0
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •TABLE 1.
- •TABLE 2.
- •AVR AT90USB82/162 Memories
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Switch
- •Exemple of use
- •Swith from external clock to RC clock
- •Switch from RC clock to external clock
- •Clock Sources
- •Default Clock Source
- •External Clock
- •Internal PLL for USB interface
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •USB Reset
- •Watchdog Timer
- •TABLE 2.
- •TABLE 2.
- •Interrupts
- •TABLE 2.
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •TABLE 3.
- •Unconnected Pins
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •TABLE 2.
- •TABLE 2.
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •TABLE 2.
- •TABLE 3.
- •TABLE 4.
- •Parity Generator
- •TABLE 3.
- •TABLE 2.
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •TABLE 2.
- •Using MPCMn
- •Receiver Flow Control
- •Overview
- •Clock Generation
- •Frame Formats
- •TABLE 2.
- •Data Transfer
- •TABLE 3.
- •USB controller
- •Features
- •Block Diagram
- •Typical Application Implementation
- •Device mode
- •Bus Powered device
- •Introduction
- •Interrupts
- •Power modes
- •Idle mode
- •Power down
- •Freeze clock
- •Memory access capability
- •Memory management
- •PAD suspend
- •D+/D- Read/write
- •Registers description
- •USB general registers
- •USB Software Operating modes
- •USB Device Operating modes
- •Introduction
- •Power-on and reset
- •Endpoint reset
- •USB reset
- •Endpoint selection
- •Endpoint activation
- •Address Setup
- •Detach
- •Remote Wake-up
- •STALL request
- •Special consideration for Control Endpoints
- •STALL handshake and Retry mechanism
- •CONTROL endpoint management
- •Control Write
- •Control Read
- •Overview
- •“Manual” mode
- •Detailed description
- •IN endpoint management
- •“Manual” mode
- •Detailed description
- •Abort
- •Isochronous mode
- •Underflow
- •CRC Error
- •Overflow
- •Interrupts
- •Registers
- •USB device general registers
- •USB device endpoint registers
- •Characteristics
- •Analog Comparator
- •Application Section
- •Boot Reset Fuse
- •Simple Assembly Code Example for a Boot Loader
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Maximum speed vs. VCC
- •Supply Current of IO modules
- •Example 1
- •Example 2
- •Example 3
- •Instruction Set Summary
- •Packaging Information
- •TQFP32
Features
•High Performance, Low Power AVR® 8-Bit Microcontroller
•Advanced RISC Architecture
–135 Powerful Instructions – Most Single Clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 16 MIPS Throughput at 16 MHz
•Non-volatile Program and Data Memories
–8K / 16K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles
–Optional Boot Code Section with Independent Lock Bits
In-System Programming by on-chip Boot Program hardware-activated after reset
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
–512 Bytes Internal SRAM
–Programming Lock for Software Security
•USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
–Complies fully with Universal Serial Bus Specification REV 2.0
–48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s
–Fully independant 176 bytes USB DPRAM for endpoint memory allocation
–Endpoint 0 for Control Transfers: from 8 up to 64-bytes
–4 Programmable Endpoints:
IN or Out Directions
Bulk, Interrupt and IsochronousTransfers
Programmable maximum packet size from 8 to 64 bytes
Programmable single or double buffer
–Suspend/Resume Interrupts
–Power-on Reset and USB Bus Reset
–USB Bus Disconnection on Microcontroller Request
–USB pad multiplexed with PS/2 peripheral for single cable capability
•Peripheral Features
–PS/2 compliant pad
–One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit PWM channels)
–One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode (three 8-bit PWM channels)
–USART with SPI master only mode and hardware flow control (RTS/CTS)
–Master/Slave SPI Serial Interface
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
–Interrupt and Wake-up on Pin Change
•On Chip Debug Interface (debugWIRE)
•Special Microcontroller Features
–Power-On Reset and Programmable Brown-out Detection
–Internal Calibrated Oscillator
–External and Internal Interrupt Sources
–Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
•I/O and Packages
–22 Programable I/O Lines
–QFN32 (5x5mm) / TQFP32 packages
•Operating Voltages
–2.7 - 5.5V
•Operating temperature
–Industrial (-40°C to +85°C)
•Maximum Frequency
–8 MHz at 2.7V - Industrial range
–16 MHz at 4.5V - Industrial range
8-bit Microcontroller with
8/16K Bytes of ISP Flash
and USB
Controller
AT90USB82
AT90USB162
Preliminary
7707A–AVR–03/07
Pin |
Figure 1. Pinout AT90USB82/162 |
Configurations |
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XTAL1 (PC0) XTAL2 GND VCC
(PCINT11) PC2 (OC.0B / INT0) PD0 (AIN0 / INT1) PD1 (RXD1 / AIN1 / INT2) PD2
AVCC UVCC |
D- / SDATA |
D+ / SCK |
UGND |
UCAP PC4 (PCINT10) |
PC5 ( PCINT9/ OC.1B) |
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QFN32 |
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(TXD1 / INT3) PD3 |
(INT5) PD4 (XCK / PCINT12) PD5 |
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(RTS / INT6) PD6 |
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HWB / T0 / INT7) PD7 |
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(SS / PCINT0) PB0 |
(SCLK / PCINT1) PB1 / MOSI / PCINT2) PB2 |
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Reset (PC1 / dW)
PC6 (OC.1A / PCINT8) PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C) PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
XTAL1 (PC0) XTAL2 GND VCC
(PCINT11) PC2 (OC.0B / INT0) PD0 (AIN0 / INT1) PD1 (RXD1 / AIN1 / INT2) PD2
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AVCC |
UVCC |
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D- / SDATA D+ / SCK UGND UCAP |
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(TXD1 / INT3) PD3 |
(INT5) PD4 |
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(XCK / PCINT12) PD5 |
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(RTS / INT6) PD6 |
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HWB / T0 / INT7) PD7 |
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(SS / PCINT0) PB0 |
(SCLK / PCINT1) PB1 |
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(CTS / |
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Reset (PC1 / dW)
PC6 (OC.1A / PCINT8) PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C) PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
Disclaimer
Note: The large center pad underneath the QFN packages is made of metal and must be connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2 AT90USB82/162
7707A–AVR–03/07