Vankka J. - Digital Synthesizers and Transmitters for Software Radio (2000)(en)

286	Chapter 15

switches, introducing a large phase modulation (PM) component. The use of the divided clocks in Figure 15-3 can cause more jitter at every other D/A converter sampling instant, which raises unwanted sideband in the bandpass mode. The PM component is reduced by shielding the D/A converter clock. Furthermore, the power supplies of the digital logic and the analog part are routed separately, while the digital and analog parts are placed to isolated wells to minimize the noise coupling to the analog output through the substrate. The last filter stage, shown in Figure 15-3, was implemented using a pipelined carry-save architecture due to the high speed requirements (see section 11.7). The taps of the folded transposed direct form FIR filters were realized with CSD coefficients. The static timing check and pre-layout timing simulations were performed for the netlist, and the chip layout was completed using Cadence place and route tools. Finally, based on the parasitic information extracted from the layout, the post-layout delays were backannotated to ensure satisfactory chip timing. Since the output of the 4:1 MUX shown in Figure 15-3 operates at f, the multiplexer has been manually designed and laid out at the transistor level. To enhance the D/A converter dynamic performance, the layout of the switch drivers and current outputs were designed as symmetrical as possible. A clock delay line was used to ensure optimal settling of switch driver control signals at the sampling instants.

15.5 On-chip Capacitor

The implemented chip features an on-chip capacitor. This section explains

DNL [LSB]

DIFFERENTIAL NONLINEARITY is 0.2119 LSB

0.5

0

-0.5	500	1000	1500	2000	2500	3000	3500	4000
		INTEGRAL NONLINEARITY is 0.2492 LSB
0.5
[LSB]
INL
0
-0.5	500	1000	1500	2000	2500	3000	3500	4000

Input Code

Figure 15-8. Typical INL and DNL.

A Digital Quadrature Modulator with on-chip D/A Converter

287

why it is needed and how it is implemented. di/dt noise results from passing a non-constant current through an inductor. In today's digital IC design this often means the inductance of bonding wires. The noise voltage is given by

	vn	(t) L	di(t)	(15.3)
			dt

The most important parameter with this noise is its peak value [Lar97].

15.5.1 Analytic First Order Model

Figure 15-9 presents the current paths in a typical CMOS circuit for an onchip and off-chip driver. The MOS transistors are modeled as switches. A simple model of di/dt noise is the triangular approximation of the current pulse with a piecewise linear shape as in Figure 15-10. The peak value is Ip and the duration is tf, the fall time of the discharged node. T is the rise time

of the current pulse to the peak value [Lar97]. The approximation gives the maximum di/dt as Ip/T and [Lar97]

	vn max L	I p	(15.4)
		T

This peak noise appears on Vss in Figure 15-9 when the output node B is switched from high to low; the same would appear on Vdd when the opposite transition occurs.

When internal circuits are switched, the noise will simultaneously appear on both Vdd and Vss, as shown by the current paths in Figure 15-9 [Lar97]. The capacitors Civ and Cig are capacitive loads connected to Vdd and Vss, respectively, whereas Cev and Ceg are capacitive loads connected to the offchip supply voltage pwr and off-chip ground gnd, respectively.

15.5.2 Negative Feedback

(15.4) predicts that the peak noise can exceed the supply voltage, which clearly does not make sense. An improved model is obtained by writing the

pwr	Civ	Vdd	Cev
+	A		B
−
	Cig
			Ceg
gnd		Vss

Figure 15-9 Current paths in a typical CMOS chip for an on-chip and an off-chip driver.

288	Chapter 15

current as a function of the noise voltage. The increase in Vss due to a falling transition in the output tends to reduce the current through the output N transistor (in Figure 15-9, the switch between Vss and the bonding wire). If it is saturated, we have

i	out	(t)	β	(																					)2	(15.5)
		2

where vin is the gate voltage of the output driver, Vt the threshold voltage and β the transconductance parameter [Lar97]. Combining this with the triangular current approximation yields for vn,max

	T		§		1 + 2(vin (T )	Vt )	Lβ ·
vn max vin (T )	Vt + Lβ		©	1			T ¹		(15.6)

15.5.3 Reducing di/dt Noise

(15.4) predicts that the peak noise depends on the peak current Ip, therefore reducing the peak current also decreases the noise [Lar97]. [Lar97] presents several techniques for reducing the peak current.

Increasing the turn on time T of the output buffer also decreases the peak noise according to (15.4). Several techniques for this have been proposed [Lar97].

(15.3) shows that the noise can be decreased by decreasing the effective inductance. A commonly utilized method is to add more bonding wires for supplying Vdd and Vss. In addition to the total inductance, the relative placement of the pins also has an impact on the reduction of di/dt noise.

vout

t

iout tf

Ip

T

t

Figure 15-10 Triangular approximation of current.

A Digital Quadrature Modulator with on-chip D/A Converter

289

Arbitrarily low levels of di/dt noise generated by internal circuits can be attained by adding decoupling capacitance between Vss and Vdd. This is discussed in next section.

15.5.4 Decoupling Capacitance

Figure 15-11 (a) illustrates the effect of decoupling capacitance Cd on the di/dt noise generated by switching output buffers. Instead of entirely going through the Vss, half the peak noise current goes through the Vdd, because the high frequency noise spike sees the decoupling capacitance as a short circuit [Lar97].

The effect of decoupling capacitance on the di/dt noise generated by switching internal circuits is illustrated in Figure 15-11 (b). The noise generated by the initial current spike can be made arbitrarily low by increasing Cd [Lar97]. The upper limit of the noise level, regarding the inductive bonding wires as open circuits, is

	Csw Vdd
2
vn max				(15.7)
	2 (Cd	Csw	)
		+
		2

where Csw is the switched capacitance [Lar97].

15.5.5 Resonance and Damping

The inductive bonding wires and the capacitance on the chip form an LC tank. Use of dedicated on-chip decoupling capacitors may cause resonance oscillations if the resonance and damping issue is not addressed [Lar98]. Figure 15-12 presents a simple second order model of a chip, it comprises the bonding wire inductances and a capacitance CT that represents the aggregate capacitance of the chip and a series resistor RT representing the aggregate resistance of the chip as defined in [Lar98]. This circuit has a resonance frequency given in (15.8) and a damping factor ζ given in (15.6) [Lar95]

pwr		Vdd		Cev	pwr		Vdd
								Civ
+	Cd	v	in	B	+	Cd	vin	B
-
				Ceg				C	ig
gnd		Vss			gnd		Vss
	(a) Output buffer					(b) Internal buffer
		Figure 15-11		Effect of decoupling capacitance Cd

290	Chapter 15

	ω res		1	(15.8)
			2LCT
	ζ	RT	CT	(15.9)
		2	2L

When a capacitance is switched during a clock cycle its charge is redistributed to the decoupling capacitance [Lar95]. The peak noise ('1' in the Figure 15-12) caused by this charge redistribution is given by (15.7). The peak to peak noise ('2' in the Figure 15-12) is given by [Lar95]

ǻVpp			§1	/	1	2	·
	vn max			+ e					(15.10)
		©					¹

Resonance can cause noise accumulation over several clock periods if the damping factor is low and the clock frequency is close to the resonance frequency. The noise accumulation can therefore be reduced by increasing damping or by using a clock frequency much lower than the resonance frequency [Lar95].

Damping can be increased by inserting a resistance in the resonance circuit. This can be accomplished in three ways: using the inherent resistance of the logic circuits, the parasitic resistance of the decoupling capacitance or the resistance of the power supply paths [Lar95]. Some other damping methods were reviewed in [Lar95] as well. Using the resistance of the logic circuits in the design of increased damping was deemed impractical in [Lar95].

The parasitic resistance of the decoupling capacitance can be designed such that a damping factor of about 0.3 to 0.4 can be attained [Lar95]. The optimal resistance of the decoupling capacitance is derived in [Lar98] to be

Rd	1		(15.11)
	ω res
		Cd

Charge	Equalizing
redistribution of G and Gnd		V				Vdd
V(Gnd)			L
				RT
1
	2			CT
		t	L
						Gnd
	over-	G
	shoot

Figure 15-12 Noise waveform of the internal Gnd node for an underdamped system when internal circuits are switched and a second order model of the chip (V and G denote the offchip supply voltage and ground respectively).

A Digital Quadrature Modulator with on-chip D/A Converter

291

SFDR (dBc) @ 0dBFS

90

fs= 150 MHz

fs= 200 MHz

fs= 250 MHz

80

70

60

500

0.1

0.2

0.3

0.4

0.5

fout/fs

Figure 15-13. SFDR as function of relative output frequency at full-scale (0 dBFS).

where Rd is the resistance of the decoupling capacitor and Cd is the capacitance. Using a single decoupling capacitor with a large resistance can cause a resistive drop in the supply voltages, if there is a very large peak current such that the inactive circuits do not have low enough resistance to supply the peak current without a substantial resistive drop [Lar95]. In this case, two decoupling capacitors can be used. One with a low parasitic resistance is used to assure low resistive voltage drop and the other is used to optimize the damping [Lar95]. Resistance of power supply paths can be used to increase the damping factor above what is typically achieved by the parasitic resistance of the decoupling capacitance.

Table 15-1. Measured D/A Converter Performance

	Resolution	12 bit
	INL	0.25 LSB
	DNL	0.21 LSB
	Full-scale output current	17.2 mA
	Sampling rate	Up to 500 MHz
	Two tone SFDR (f = 150 MHz,	58.7 dBc
	fout1 = 39.75 MHz, fout2 = 45.75 MHz)
	Power consumption (f = 500 MHz)	240 mW
	Process	0.35 m CMOS
	D/A converter core area	3.73 mm2

292	Chapter 15

15.5.6 Implemented On-chip Capacitor

In high performance systems, a fair share of the chip area is consumed by the on-chip capacitors. [Che95] reports that about 10% is needed for high per-

	M arker 1 [T1]		RBW 30	k	z	R Att	10 d
Ref Lvl	19 11	dB m	VBW 30	kHz		Mixer	20 dB
10 dBm	7.69803607	MHz	SWT 76	ms		Unit	dBm
-10	LIMIT CHECK : PASSED

-20

-30

-40

1AVG

-50

-60 -70 -80

-90 EDGE_SPEC

-100

-110

Center 7.68 MHz

360

kHz/

Span 3.6 MHz

Figure 15-14. Power spectrum of the EDGE signal in the lowpass mode.

			Marker 1 [T1]		RBW		30 kHz			R F Att 10 dB
	Ref	Lvl	-62.98	dBm	VBW 30 kHz					Mixer -10 dBm
36.1		dBm	117.58000000	MHz						Unit	dBm
						SWT	74 ms

6.

3

8 dB

Offse

dBm

1

[T1]

2.98

117.58

000000

MHz

CH

PWR

20.21

dBm

ACP

Up

-

60.06

dB

ACP

Low

-60.59

dB

ALT1

Up

-61.90

dB

1A

V

ALT1

Low

-62 64

dB

-

-

-

-
-	cI2	cI2

cI1

-1

-
-73.9 Center	130.58 MHz

C0	C0
cI1
	cu1	cu1
			cu2
		cu2
6 M		Span	26 MHz

Figure 15-15. Power spectrum of the WCDMA signal in the bandpass mode.

A Digital Quadrature Modulator with on-chip D/A Converter

293

formance circuits with a cycle time of 5 ns or less. Therefore, on-chip decoupling capacitors (total capacitance of 2 nF) are used in Figure 15-17 and Figure 16-22. The capacitor units consist of two overlapping metal layers. Instead of one big capacitor, it is better to insert smaller capacitors close to the hot spots of the chip, where the intense switching activity would otherwise bring about excessive power supply noise. In these circuits, the inductance of the bond wire is small, because the ground level is connected through several bonding wires and package pins.

15.6 Measurement Results

The orthogonal carriers to the digital quadrature modulator are generated by the multistandard modulator [Van02] in measurements. The on-chip D/A converter was used in measurements. Measurements are performed with a 50 Ω doubly terminated cable. Figure 15-8 shows that typical INL and DNL errors are 0.25/0.21 LSB, respectively. Figure 15-13 shows the spurious free dynamic range (SFDR) as a function of relative output frequency. The digital quadrature modulator was bypassed in the SFDR measurements (Fig. 10), because the output frequency response of the digital quadrature modulator

											CF		130.56	MHz
																		Symbol/Errors
Ref Lvl												SR	270.833	kHz
	-11 dBm																	Standard	GSM
							Symbol	Table
																						A
		0	01110101		01000000	01110010		11111011					11100111
		40	11101101		01111110	11011010		00111101					11011010
		80	00001000		01010110	01000100		00111100					00010111
		120	11100000		01111000	11101110		0000

										Error Summary
			Error Vector Mag					0.56	%	rms	1.58			%	Pk	at	sym	96
		Magnitude Error						0.17	%	rms	0.50			%	Pk	at	sym	141
				Phase			Error	0.31	deg rms		0.91			deg Pk at			sym	96
			Freq				Error	-15.17		Hz	-15.17			Hz	Pk
	Amplitude Droop							0.06	dB/sym		Rho Factor						1.0000
				IQ Offset				0.20	%		IQ Imbalance						0.03 %
Date						:	22.AUG.2002	13:28:58

Figure 15-16. Measured phase and frequency errors.

294	Chapter 15

has only lowpass, bandpass and highpass modes (see Figure 15-4). The data was driven directly to the D/A converter. The maximum operation frequency of the input pads was 250 MHz, which is the highest sampling frequency in Figure 15-13. The D/A converter performance is summarized in Table 15-1.

The digital quadrature modulator is designed to fulfill the derived spectral, phase, and EVM specifications of GSM, EDGE and WCDMA base stations. The EDGE output signal in the lowpass mode fulfills the EDGE spectrum mask requirements set out in Figure 15-14 [GSM99]. Figure 15-15 shows the WCDMA output with a crest factor of 8.48dB in bandpass mode, where the adjacent channel leakage powers (ACLR1/2) are 60.06 and 61.90dB, respectively, which fulfill the specifications (45/50 dB) [FDD00]. The ACLR1/2 are 77.07 and 82.12dB at the D/A converter input, so most of the errors are generated less by quantization errors in the digital domain and more by the D/A converter analog non-idealities. Figure 15-16 shows the phase error performance of the GSM signal, where the measured phase error is 0.31 rms with a maximum peak deviation of 0.91 . The phase error specifications are 5 with a peak of 20° [GSM99]. The phase error is low, because the quadrature modulation is performed digitally with high precision. The D/A converter sampling frequency was 491.52MHz in the figures.

15.7 Conclusion

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs f /4, -f /4, f /2 digital quadrature modulation. A

Figure 15-17. Chip microphotograph

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295

12b D/A-converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and enhance dynamic performance. The die area of the chip is 27.09 mm2 (0.35 m CMOS technology). Total power consumption is 1.02W at 2.8V with 500MHz (0.78W digital modulator, 0.24W D/A converter). The IC is in a 160-pin CQFP package. Figure 15-17 displays the chip microphotograph.

REFERENCES

[Bas98] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12bit Intrinsic Accuracy High-Speed CMOS DAC," IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 1959-1969, Dec. 1998.

[Bos01]A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter," IEEE J. Solid-State Circuits, Vol. 36, No. 3, pp. 315-324, Mar. 2001. [Che95] H. H. Chen, and S. E. Schuster, "On-Chip Decoupling Capacitor Optimization for High-Performance VLSI Design," in Proc. International Symposium on VLSI Technology, Systems, and Applications, 1995, pp. 99-

103.

[Chi94] S. Y. Chin, and C. Y. Wu, "A 10-bit 125-MHz CMOS Digital-to- Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources," IEEE J. of Solid State Circuits, Vol. 29, No. 11, pp. 1374-1380, Nov. 1994.

[Dar70] S. Darlington, "On Digital Single-Sideband Modulators," IEEE Trans. Circuit Theory, Vol. 17, No. 3, pp. 409-414, Aug. 1970.

[FDD00] 3rd Generation Partnership Project; Technical Specification Group Radio Access Networks; UTRA (BS) FDD; Radio transmission and Reception, 3G TS 25.104, V3.3.0, June 2000.

[GSM99] GSM Recommendation 05.05: "Radio Transmission and Reception," Dec. 1999.

[Kos01]M. Kosunen, J. Vankka, M. Waltari, and K. Halonen, "A Multicarrier QAM Modulator for WCDMA Basestation with on-chip D/A Converter," Proceedings of CICC 2001 Conference, May 6-9 2001, San Diego, USA, pp. 301-304.

[Lar95] P. Larsson, "Analog Phenomena in Digital Circuits," Ph.D. dissertation, No. 376, Linköping University, Linköping, Sweden, 1995.

[Lar97] P. Larsson, "di/dt Noise in CMOS Integrated Circuits," Analog Integrated Circuits and Signal Processing, Vol. 14, pp. 113-129, Sept. 1997. [Lar98] P. Larsson, "Resonance and Damping in CMOS Circuits with OnChip Decoupling Capacitance," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 8, Aug. 1998, pp.

849-858.