ARM PrimeCell™ MultiPort Memory
Controller (PL172)
Technical Reference Manual
Copyright © 2002 ARM Limited. All rights reserved.
ARM DDI 0215A
ARM PrimeCell MultiPort Memory Controller (PL172)
Technical Reference Manual
Copyright © 2002 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this document.
Change history
Date |
Issue |
Change |
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January 2002 |
A |
First release |
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Proprietary Notice
Words and logos marked with © or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Confidentiality Status
This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final (information on a developed product).
Web Address
http://www.arm.com
ii |
Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |
Contents
ARM PrimeCell MultiPort Memory Controller
(PL172) Technical Reference Manual
Preface
|
|
About this document .................................................................................... |
xiv |
|
|
Feedback ................................................................................................... |
xviii |
Chapter 1 |
Introduction |
|
|
|
1.1 |
About the ARM PrimeCell MultiPort Memory Controller (PL172) ................ |
1-2 |
|
1.2 |
Supported dynamic memory devices .......................................................... |
1-4 |
|
1.3 |
Supported static memory devices ............................................................... |
1-6 |
Chapter 2 |
Functional Overview |
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|
|
2.1 |
PrimeCell MPMC functional description ...................................................... |
2-2 |
|
2.2 |
Overview of a PrimeCell MPMC, ASIC, or ASSP system ......................... |
2-10 |
|
2.3 |
Low power operation ................................................................................. |
2-12 |
|
2.4 |
Lock and semaphores ............................................................................... |
2-13 |
|
2.5 |
Arbitration .................................................................................................. |
2-14 |
|
2.6 |
Memory bank select .................................................................................. |
2-15 |
|
2.7 |
Memory map ............................................................................................. |
2-16 |
ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
iii |
Contents
Chapter 3 |
Programmer’s Model |
|
|
|
3.1 |
About the programmer’s model .................................................................. |
3-2 |
|
3.2 |
Register descriptions .................................................................................. |
3-7 |
Chapter 4 |
Programmer’s Model for Test |
|
|
|
4.1 |
PrimeCell MPMC test harness overview .................................................... |
4-2 |
|
4.2 |
Scan testing ................................................................................................ |
4-3 |
|
4.3 |
Test registers .............................................................................................. |
4-4 |
Chapter 5 |
Static Memory Controller |
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|
5.1 |
Static memory device selection .................................................................. |
5-2 |
|
5.2 |
Write-protection .......................................................................................... |
5-3 |
|
5.3 |
Extended wait transfers .............................................................................. |
5-4 |
|
5.4 |
Memory mapped peripherals ...................................................................... |
5-5 |
|
5.5 |
Static memory initialization ......................................................................... |
5-6 |
|
5.6 |
Byte lane control ....................................................................................... |
5-23 |
5.7Byte lane control and databus steering for little and big-endian configurations 5-28
Chapter 6 |
Dynamic Memory Controller |
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|
|
6.1 |
Write-protection .......................................................................................... |
6-2 |
|
6.2 |
Access sequencing and memory width ...................................................... |
6-3 |
|
6.3 |
Address mapping ........................................................................................ |
6-4 |
|
6.4 |
Dynamic memory controller command descriptions ................................. |
6-53 |
|
6.5 |
Generic SDRAM initialization example ..................................................... |
6-54 |
|
6.6 |
Micron MT48LC4M16A2 SDRAM initialization example .......................... |
6-56 |
|
6.7 |
Low-power SDRAM initialization example ................................................ |
6-59 |
|
6.8 |
Micron MT28F4M16S2 SyncFlash initialization example ......................... |
6-62 |
|
6.9 |
Micron SyncFlash commands .................................................................. |
6-64 |
Chapter 7 |
Common Memory Transactions |
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|
7.1 |
Static and dynamic memory transaction latency ........................................ |
7-2 |
Chapter 8 |
Test Interface Controller |
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|
8.1 |
About TIC ................................................................................................... |
8-2 |
|
8.2 |
Sequence of events leading to entry into TIC test mode ............................ |
8-3 |
Chapter 9 |
System Connectivity |
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9.1 |
On-chip signals ........................................................................................... |
9-2 |
|
9.2 |
Self-refresh entry ........................................................................................ |
9-6 |
|
9.3 |
Example system ....................................................................................... |
9-10 |
iv |
Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |
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Contents |
Chapter 10 |
Off-chip Connectivity |
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10.1 |
Off-chip signals ......................................................................................... |
10-2 |
|
10.2 |
Pin count reduction by reducing databus width ......................................... |
10-4 |
|
10.3 |
Pin count reduction by removing functionality ........................................... |
10-5 |
|
10.4 |
Address pin reduction ............................................................................... |
10-9 |
|
10.5 |
Chip select pin reduction ......................................................................... |
10-10 |
|
10.6 |
Device support ........................................................................................ |
10-11 |
|
10.7 |
Multiplexing static and dynamic memory pins ......................................... |
10-12 |
|
10.8 |
Reducing pin count by multiplexing MPMC pins ..................................... |
10-13 |
|
10.9 |
About MPMC timing ................................................................................ |
10-14 |
|
10.10 |
On-chip timing path ................................................................................. |
10-15 |
|
10.11 |
Off-chip timing path ................................................................................. |
10-16 |
|
10.12 |
Clock strategy ......................................................................................... |
10-17 |
|
10.13 |
Clock ratios ............................................................................................. |
10-18 |
|
10.14 |
Memory clock and fed-back clock strategy ............................................. |
10-19 |
Appendix A |
Pad Interface Timing |
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|
A.1 |
Overview ..................................................................................................... |
A-2 |
|
A.2 |
Signal delay ................................................................................................ |
A-3 |
|
A.3 |
Method to reduce delay .............................................................................. |
A-4 |
|
A.4 |
Methods to reduce skew ............................................................................. |
A-6 |
|
A.5 |
Methods to minimize the effects of delay and skew .................................... |
A-7 |
|
A.6 |
Example SDRAM memory timing diagram .................................................. |
A-8 |
|
A.7 |
SDRAM memory timing paths ..................................................................... |
A-9 |
Appendix B |
Troubleshooting |
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|
B.1 |
Troubleshooting .......................................................................................... |
B-2 |
Appendix C |
MultiPort Memory Controller Signal Descriptions |
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C.1 |
AHB register signals .................................................................................. |
C-2 |
|
C.2 |
AHB memory signals .................................................................................. |
C-4 |
|
C.3 |
Miscellaneous and clock signals ................................................................ |
C-6 |
|
C.4 |
Pad interface and control signals ............................................................... |
C-8 |
|
C.5 |
Test Interface Controller (TIC) signals ..................................................... |
C-12 |
|
C.6 |
Scan test signals ...................................................................................... |
C-14 |
ARM DDI 0215A |
Copyright © 2002 ARM Limited. All rights reserved. |
v |
Contents
vi |
Copyright © 2002 ARM Limited. All rights reserved. |
ARM DDI 0215A |