Atmel applications journal.Spring 2004

A T M E L A P P L I C A T I O N S J O U R N A L

gle room, and operates at up to 11 Mbps. Data transmission at 54 Mbps is becoming possible as enhanced versions of the IEEE 802.11 standard are adopted. Any compatible device coming within radio range can be integrated automatically into the network, with no configuration operations required.

IEEE 802.11 Standards

A number of variants of the IEEE 802.11 standard are in operation, under development or in discussion:

•The basic 802.11b standard operates in the unregulated 2.4 GHz ISM (Industrial, Scientific and Medical) band. It provides data transmission rates up to 11 Mbps and incorporates an encryption standard called Wired Equivalent Privacy (WEP).

•The high-throughput 802.11a standard operates at 4.9 GHz to 5.85 GHz with a maximum data rate of 54 Mbps. It uses a different data encoding technique (modulation) from the 802.11b, in order to achieve the higher data rate.

•The high-throughput 802.11g standard operates at 2.4 GHz but uses a combination of both the .11a and .11b encoding techniques to achieve data rates of up to 54 Mbps.

•The multimedia 802.11e standard that is expected to be ratified soon and incorporates Quality of Service (QoS) in order to be useful for multimedia applications such as high-quality sound or video streaming. Prioritized traffic is a key feature of this standard.

•The enhanced-security 802.11i standard, expected to be ratified soon and, includes higher-level security measures such as TKIP (a WEP enhancement), the 802.1x authentication and key exchange mechanism and the

Advanced Encryption Standard (AES), an existing Federal Information Processing Standard from the US Government.

All these variants operate in unregulated radio frequency bands. Provided that the transmitters conform to the maximum power limitations, no authorization is required to use them.

Wi-Fi Alliance

The Inter-operability of wireless LAN products following the IEEE 802.11 set of standards is certified by the Wi-Fi Alliance (previously known as the Wireless Ethernet Compatibility Alliance (WECA)). Wi-Fi certified products carry a stamp of approval indicating that they have passed the Inter-operability tests in the Wi-Fi Alliance laboratories. See Figure 4.

and their supporting circuits in order to be able to make the physical (radio) connection and to support the communications protocol. The ICs usually found in any Wireless LAN device are:

•the Media Access Controller (MAC) supporting the communications protocol (generally fabricated in CMOS)

•the Baseband Controller (BB) that implements the modulation/demodulation scheme required for the PHY layer (Power Amplifier and FR Transceiver) running in either 2.4 or 5 GHz (usually CMOS)

•the Power Amplifier (PA) usually fabricated in Gallium Arsenide (GaAs) or BiCMOS

•the Radio Frequency (RF) Transceiver IC for the implementation of the RF functions for the Wireless LAN (usually SiGe BiCMOS).

Some solutions have the MAC-plus-BB on the same chip, usually in CMOS. A Wireless LAN design is accompanied from a number of internal or external memories for storing of data and program code (SRAM, EEPROM, Flash, etc.). This white paper concentrates on Atmel’s family of MACs for wireless LANs, specifically the AT76C503A USB Wireless LAN MAC.

AT76C503A Architectural Overview

The AT76C503A is built around the Advanced System Bus (ASB) and (Advanced Peripheral Bus (APB) structures of an embedded ARM7TDMI® 32bit RISC microcontroller. It integrates dedicated modules for memory interfacing, USB control, wireless PHY interfacing and data encryption/decryption using Wired Equivalent Privacy, as well as two system timers and an interrupt controller for support functions. A decoder/arbiter/bridge module links the two buses. See Figure 5.

Figure 4: The Wi-Fi Alliance Logo and the WiFi Certification Mark

Wireless LANs are being set up in offices and campuses, and in an increasing number of public spaces such as cafes. A wireless LAN in a public space is referred to as a hotspot. For example, the city of Singapore is in the process of installing a series of overlapping hotspots covering the entire urban area. IEEE 802.11b is at present the dominant standard for Wireless LANs.

The Wi-Fi Alliance recently announced its own standards-based security solution called Wi-Fi protected Access (WPA) to enhance WEP. This security solution is actually a subset of the IEEE 802.11i draft standard, retaining the TKIP and 802.1x but not the AES specification. The intention of the Wi-Fi Alliance is to cover the immediate market needs for enhanced security while giving time to IEEE to finalize the full robust IEEE 802.11i standard.

Integrated Circuits for Wireless LAN Connectivity

Any device that connects to a wireless LAN requires a number of dedicated ICs

Figure 5: AT76C503A Architecture

The high-speed ASB makes optimal use of the data processing bandwidth of the ARM7TDMI core, while the lower-speed APB keeps power consumption to a minimum for non-time-critical functions. This combination of bus structures, as well as the use of dedicated FIFO (first-in, first-out) buffers and DMA (direct memory access) for data transfers, enables the AT76C503A to achieve the data throughput rates required for its USB and WLAN Interfaces (12 Mbps and 11 Mbps, respectively) while minimizing power consumption at the same time.

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Wireless LAN ARM® Core (WLAN ARM)

The embedded ARM7TDMI 32-bit RISC microcontroller core performs overall system control as well as implementing the software stacks for the wireless protocol supported (such as IEEE 802.11b) and for the USB. The industry-lead- ing ARM7TDMI core is well suited to these tasks due to its high instruction and data throughput (approaching 1 MIPS per MHz). The interrupt controller that enables it to switch tasks in response to interrupts in only a few clock cycles enhances its real-time performance.

The key architectural feature of the ARM7TDMI is its banked register file containing 31 32-bit registers. These store the operands and results for most data manipulation instructions, enabling these to be executed in a single clock cycle. See Figure 6.

References

1.TechFest Ethernet Technical Summary, Web: http://www.techfest.com/networking/lan/ ethernet.htm

2.Wi-Fi Alliance (previously Wireless Ethernet Compatibility Alliance (WECA)),

Web: http://www.weca.net

3.Edward C. Prem: Wireless Local Area Networks, Web: ttp://www.netlab.ohiostate. edu/~jain/cis788-97/wireless_lans/index.htm

4.Wireless-Nets Consulting Services, Web: http://www.wireless-nets.com/

5.Spread Spectrum Scene, Web: http://

sss-mag.com/wlan.html

6. Virtual Private Networking: An Overview, Web: http://www.microsoft.com/windows 2000/techinfo/howitworks/communications/ remoteaccess/vpnoverview.asp

Figure 6: ARM7TDMI 32-bit RISC Microcontroller Architecture

An additional benefit of the ARM7TDMI is its Thumb“ operating mode where frequently-used instruction codes are compressed to 16 bits, thereby halving the code memory requirement. Thumb opcodes are de-compressed to 32 bits for execution in real time, with no performance degradation. The ARM7TDMI operating mode can be changed at run-time with negligible overhead.

Memory configuration data and registers in the on-chip operational modules (Memory Interface Controller, USB Controller, WEP and WPAI) and peripherals (Interrupt Controller and System Timers) are accessible within the address space of the ARM7TDMI. This enables their configuration and operation to be easily controlled by software running on the ARM7TDMI core.

Memory Interface Controller

The Memory Interface Controller (Figure 7) regulates access to both on-and off-chip memories. The combination of off-chip memories can be optimized by both size and composition according to the specific requirements of the application. Each memory block has a dedicated region in the ARM7TDMI core address space.

The Internal Memory Interface accesses the on-chip ROM and SRAM blocks. The ROM is pre-loaded with the USB control software that automatically configures the USB interface when the device is connected. The ROM also contains

Figure 7: AT76C503A USB Controller

a device firmware upgrade module that enables firmware to be uploaded into internal SRAM. The 6K x 32-bit internal SRAM is loaded with all software modules that require intensive access. It shadows the external Flash in order to keep instruction access time to a minimum. The internal SRAM also holds all working data and stacks.

The External Memory Interface (EMI) provides byte-wide access to up to 16M bytes of external SRAM and 16M bytes of external Flash. The Flash memory contains the AT76C503A firmware while the SRAM holds the ARM7TDMI core stack, AT76C503A firmware status variables, data structures supporting the host/firmware interface and network data buffers.

USB Controller

The AT76C503A communicates with a host (generally a PC) through a fullspeed (12 Mbps) USB port (Figure 8). It includes a dual-port RAM (DPRAM) buffer connected to the ASB and consists of four functional elements:

•The Serial Interface Engine (SIE) performs the front-end clock/data separation, NRZI encoding and decoding, bit insertion and deletion, CRC generation and checking and serial-parallel data conversion.

•The Function Interface Unit (FIU) manages the USB endpoint buffers and controllers for seven different endpoints. The endpoint buffers consist of dedicated FIFOs, mostly double-buffered.

•The Serial Bus Controller (SBC) manages the device addresses, monitors the status of the transactions, manages the FIFOs and communicates with the ARM7TDMI core through a set of control and status registers.

•The System Interface (SI) connects the Serial Bus Controller to the ARM7TDMI core and provides a DMA (direct memory access) mechanism for transferring data between the DPRAM and the endpoint buffers.

The USB port supports the Suspend mode for reducing power consumption.

Wired Equivalent Privacy (WEP) Module

Wired Equivalent Privacy (WEP) is part of the IEE 802.11 standard. This service is intended to provide security for the wireless LAN equivalent to that pro-

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A T M E L A P P L I C A T I O N S J O U R N A L

Figure 8: AT76C503A USB Controller

vided by the physical security attributes inherent in a wired medium. It is based on the RSA’s RC4 symmetric, 64or 128-bit single-key encryption/decryption algorithm together with a 32-bit cyclic redundancy check (CRC-32) checksum.

The AT76C503A incorporates a hardware WEP module that encrypts/decrypts outgoing and incoming data streams in real time. It is connected directly to the WPAI transmission and reception FIFOs described below. This causes no delays in signal transmission/reception and thus no performance degradation even with 128-bit encryption.

WEP is considered mandatory for all Wireless LAN networks, but higher-level security procedures such as VPN (Virtual Private Network) or MAC Filtering are recommended for protection against expert intruders. Higher-level security can be provided by a suitable algorithm running in the ARM7TDMI core, or by an external crypto co-processor. More robust security will be provided from the implementation of the algorithms and procedures included in the Wi-Fi Alliance's WPA specification and later when the IEEE 802.11i standard is finalized and implemented.

Interrupt Controller

The Interrupt Controller enhances the interrupt handling mechanism of the ARM7TDMI core. It handles interrupt prioritization and scheduling and enables the ARM7TDMI core to branch to an interrupt handler in only a few clock cycles.

AT76C503A Operating Modes and Clock Configurations

The AT76C503A supports several different modes of operation according to the implementation required. One significant advantage of the design is the fact that the external Parallel Flash can be omitted and the firmware can be downloaded into the internal memory directly from the USB interface, by running the DFU protocol from an internal bootstrap ROM.

System Firmware

The system firmware running on the AT76C503A hardware provides all the functionality required for implementing a glueless, high-speed interface to wireless networks implementing a protocol such as the IEEE 802.11b.

The system firmware, available from Atmel to qualified customers, includes a real-time operating system (RTOS) micro-kernel and drivers for all the required support functions including:

•Distributed Coordination Function (DCF) as specified in IEEE 802.11b

•WEP encryption/decryption

•USB interface functionality

•Power management

Supported operating systems include Microsoft® Windows® 9x/Me/ 2000/XP, Windows NT® 4.0, and Windows CE 3.0/PocketPC OSs, Linux® 2.0.x for Intel® processors. For all operating systems where Microsoft WHQL certification exists, the drivers provided by Atmel are in a WHQL-certifiable state.

The source code for the Linux drivers is available under the General Purpose License (GPL) from http://atmelwlandriver.sourceforge.net.

A simple AT76C503A device driver is required on the host system.

Evaluation and Development Tools

Wireless Physical Attachment Interface (WPAI)

The Wireless Physical Attachment Interface (WPAI) provides the direct interface with the external Wireless PHY module. It contains 128-byte transmit and receive FIFOs that communicate with other memories by direct memory access (DMA). This relieves the ARM7TDMI core of the detailed management of these transfers, leaving it free for higher-level operations.

The WPAI module is designed to automate many time-critical physical network management tasks. It implements primitives for efficient 802.11b MAC protocol implementation at 11 Mbps with automatic fallback to 5.5, 2 and 1 Mbps. It also provides a 64-bit Time Synchronization Function (TSF) counter as specified by the 802.11 protocol, and supports automatic defer when the wireless medium is occupied while a transmission is pending.

Decoder/Arbiter/Bridge

The Decoder/Arbiter/Bridge unit links the high-speed WLAN ASB to the ener- gy-efficient APB, and permits elements other than the ARM7TDMI core to act as bus masters. It is a key element in the overall energy efficiency of the AT76C503A.

System Timers

The AT76C503A incorporates two independent system timers. Each has programmable pre-scale and pre-load capabilities allowing it to produce periodic or one-shot interrupts. The system timers can be used to implement IEEE 802.11 protocol functions such as virtual medium allocation, periodic beacon production or power management.

Comprehensive evaluation and development tools are available from Atmel to facilitate application development based on the AT76C503A. (See Figure 9).

These include all the required elements:

•AT76C503A/USB evaluation or development board with USB cables

•RFMD™ based radios and antenna

•System firmware (object code) as described before

•Software utilities for application development

•Comprehensive User Guide.

Figure 9: AT76C503A Evaluation Board

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A T M E L A P P L I C A T I O N S J O U R N A L

Application Examples

Linksys® WUSB11 V2.6 Instant Wireless USB Network Adapter

TOne of the first products to adopt the AT76C503A is the Linksys“ WUSB V2.6 Instant Wireless‘ USB Network Adapter (Figure 10). Equipped with USB cabling and software driver, it provides a plug-and-play Wireless LAN connection for a desktop or portable PC fitted with a USB port and running Microsoft Windows 98/SE/ME/2000 or XP. Implementing the IEEE 802.11b protocol, it supports data transfer rates up to 11 Mbps. The WUSB11 V2.6 is Wi-Fi Certified.

iPAQ® h5400 Pocket PC

The iPAQ® h5400 Pocket PC from HP® (Figure 11) is a multimedia PDA that integrates wireless LAN connectivity using the AT76C503A. It takes advan-

h5400	is Atmel’s
A T 7 7	C 1 0 1 B

FingerChip™ for biometric login authentication. It relieves the user of the task of memorizing and updating login passwords, and makes it almost impossible for a lost or stolen device to be used by someone else.

Conclusion

Figure 11: HP iPAQ h5400 Pocket PC with AT76C503A for Wireless LAN Connectivity

Atmel’s AT91 ARM® Thumb®--Everywhere You Are

Atmel's AT91 ARM Thumb microcontrollers provide the 32-bit performance every 8-bit microcontroller user is dreaming of while staying within his tight system budget. The extra performance enables the implementation in software of innovative but evolving protocols for communication, compression or control.

Building a microcontroller product line around the industry-standard ARM processor core guarantees the customer long-term availability, and its widespread acceptance has resulted in the development of an extensive range of qualified software IP products reducing the time-to-market

for new AT91 low-power, already been

tems, MP-3/WMA players, Data Acquisition products, Pagers, Point-of-Sales terminals, Medical equipment, GPS and Networking systems.

The AT91 series is completely supported by state-of-the-art development tools, including C-compilers, Debuggers, Emulators and RTOS.

Start your journey today towards a successful design at: www.atmel.com/arm

Eval Board	Microprocessor Supported
AT91EB40	Supports AT91X40, enabling code development & eval.
AT91EB40A	Supports AT91RO40008, enabling code development & eval.
AT91EB42	Supports AT91M42800A, enabling code development & eval.
AT91EB55	Supports AT91M55800A, enabling code development & eval.
AT91EB63	Supports AT91M63200 & AT91M43300
	enabling code development & eval.

Memory Extension Card

AT91MEC01

Increases memory capacity of AT91 Eval. Board, adding 2M bytes of SRAM and 3M bytes of Flash on the external bus.

Complete with application Guide.

R

© 2003 Atmel Corporation. Atmel and the Atmel logo are registered trademarks of Atmel Corporation.

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A T M E L A P P L I C A T I O N S J O U R N A L

As thet semiconductori t processes transitionst iti toto deep sub--microni lithography,lit , supplyly voltageslt need toto be reduced accordinglyi ly.. The transitiont iti fromf

5 voltlt tolerantt l t systemst toto 3 voltlt systemst isis acceleratingl ti inin thet currentt markett place,l ,

however nott allll compo-- nentsts have migratedi t toto thet lowerl voltageslt and systemt designersi are encounteringt i difficultyiffi lty specifyingif i thet e entiree ti e bill billof materialsof materialsin a insinglea singlepower powersupplysupplyrange. range.

Interfacing the 3 Volt DataFlash™ with a 5 Volt System

by Dirk Franklin, Atmel

As the semiconductor processes transitions to deep sub-micron lithography, supply voltages need to be reduced accordingly. The transition from 5 volt tolerant systems to 3 volt systems is accelerating in the current market place, however not all components have migrated to the lower voltages and system designers are encountering difficulty specifying the entire bill of materials in a single power supply range. This is an even greater problem for companies facing maintenance of legacy systems and spares sourcing where complete redesigns are not practical but at the same time due to obsolescence the original parts are not available in the original supply voltage range.

Atmel has kept this in mind when designing the AT45DBxxxB series, 3 Volt only DataFlash family. The 3 Volt DataFlash Family can be used in 5 Volt Systems. This applications note endeavours to discuss the conditions of using a 3 Volt DataFlash devices in a 5 Volt system or systems with mixed voltage environments.

AC Characteristics and Operational Conditions

Supply Voltage Requirements

The power supply to the DataFlash device must be between 2.7V and 3.6V for correct operation. Exceeding these levels may result in incorrect operation or damage to the device. Max ratings are shown in the AC Characteristics and Max ratings tables in the datasheets.

Logic Level Definitions

The majority of systems today conform to one or two logic interfacing standards, these being TTL or CMOS. It is therefor necessary to consider the effects of interfacing a 3 Volt Dataflash to a 5 Volt system that is either CMOS or TTL compatible

TTL Logic Levels

The minimum VIH requirement of a TTL compatible input is 2.0V to register a logic 1, and the VIL requirement of a TTL compatible input is 0.8V to register a logic 0. Refer to the manufacturers datasheet to ensure full compliance with the Input and output logic level requirements.

	Dataflash Input Pins
• SI	Serial Data In
• SCK	Serial Clock
• /CS	Chip Select
• Reset	Reset input
• /WP	Write Protect

	DataFlash Output Pins
• SO	Serial Data Out

• SO0 – SO7 Data Out bit 7 through bit 0

• RDY/BSY Ready Busy Signal

This applications note will only consider Serial Data mode. The parallel data mode option is not available on all devices.

of the device and is not discussed in this application note.

Driving a TTL compatible load

A DataFlash driving into a TTL compatible input will meet minimum TTL input logic level requirements. The DataFlash output will drive to VCCDF – 0.2V, therefore under worst case or lowest VCCDF conditions the minimum output level achievable by the DataFlash will be VOH=2.7V-0.2V = 2.5V. Figure 1 illustrates a typical system where the DataFlash is driving a TTL Compatible

Figure 1: TTL Compatible Device Interface Diagram

CMOS Logic Levels

The minimum VIH requirement for a CMOS compatible input is 0.7 x VCC to register a logic 1, where VCC is the supply voltage of the input device. For a CMOS device operating with a VCC of 4.5V to 5.5V this gives a VIH requirement of 3.15V to 3.85V. The VIL requirement of a CMOS compatible input is 0.2V to register a logic zero.

System Considerations and Problem Definition

To fully review the implications of operating a 3V DataFlash device in a 5V system, two aspects need to be considered:

1.Device Input and Output Level requirements.

2.Voltage Regulation to the Dataflash

Device Input and Output Level requirements

The DataFlash input pins are tolerant to 5 Volt input levels and will not present a problem in either CMOS or TTL compatible systems. The input and output pins for the DataFlash are shown top righ column:

The output pins however will only operate within the specification of the DataFlash and the limits of the VCCDF power supply. The Dataflash has one output pin in Serial Mode and 8 output pins in Parallel data mode. The RDY/BSY signal is an open collector output which indicates the current status

load.

Driving a CMOS compatible load

A problem arises when considering the Output drive levels provided by the Serial Output pin (SO) of a Dataflash when driving into a CMOS compatible interface. A standard 5V compatible CMOS input requires a VIH input of 3.15V minimum, greater than the output drive level a Dataflash can provide under worst-case conditions. As the Output of the DataFlash is not capable of driving a 5V CMOS load directly a level shifter or alternative method of translating the DataFlash output logic levels to those compatible with the input device is required. Figure 2. Illustrates the requirement for a level shifter in the Serial

Figure 2: CMOS Compatible Interface Diagram

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Figure 3: Voltage Regulator Diagram

A T M E L A P P L I C A T I O N S J O U R N A L

Data Output signal of the Dataflash when driving a 5V compatible CMOS input.

Voltage Regulation

Few systems will provide both 5V and 3V regulated VCC rails in the same circuit, therefore a system or method to step down and regulate the voltage to the Dataflash is required. The choice of voltage regulator depends on the host system power supply characteristics, the maximum current drawn by the dataflash device, and the costs associated with adding a voltage regulator. In legacy systems this may also require additional thought towards the practical implementation of the chosen solution.

Programming Current

It is essential to consider the maximum current requirements of the Dataflash when selecting an appropriate method of voltage regulation. Maximum load or peak current draw occurs when the Dataflash is in programming or erase mode and will range from 70mA to 80mA. It is also important to consider RMS current requirements of the DataFlash during these operations. Current starvation will increase noise in the whole system and also lead to the incorrect operation and possible data corruption in the dataflash device during programming or erase operations.

System Solutions

By ensuring that the input signals to the Dataflash remained 5 volt tolerant, Atmel has minimised the overall impact of these essential process and device changes on end applications and customers. However two issues have been identified in the discussion above when attempting to use a Dataflash device in a 5V system as follows:

•A secondary Voltage Regulator will be required when using a Dataflash in a 5V system

•A Level Shifter will be required to translate the output logic level of a DataFlash output when used in a 5V CMOS compatible system.

Practical and workable solutions for these two issues will be wide ranging and many innovative solutions will be found. The fol-

lowing section will look at a some of the more conventional possibilities.

Voltage Regulation Solutions

Many off-shelf-voltage regulators or DC to DC converters exist today that would provide the DataFlash with a 2.7V to 3.6V regulated VCC supply from an input supply range of 4.5V to 5.5V. Figures 3 and 4 illustrate a typical voltage regulator solution utilising a Linear Technology LT1761 series Low Drop Out, Low

Noise regulator. Other solutions could be implemented using a wide range of single chip voltage regulators or converters available from different manufacturers. Table 1 provides a short list of semiconductor manufacturers offering voltage regulators or DC/DC converters suitable for this application. Any voltage regulator based design would need to consider current delivery requirements and may require additional external components such as capacitors, resistors or inductors to ensure correct operation, regulation and current delivery. Please consult appropriate vendors datasheets and applications notes on the individual component specifications.

Figures 5 and 6 illustrate a simple three-diode regulator scheme. The thresh-

Figure 4: Example Voltage Regulator Solution

Figure 5: Example of a Simple Diode

Voltage Regulator

old voltage (Vt = 0.7V apx.) for each diode would contribute to a total series voltage drop across the circuit of 2.1Volts. The advantage to this kind of regulation scheme is cost and space. One limitation of this circuit is the input voltage range, which must remain at or above 4.8V to ensure a minimum supply at the DataFlash remains above 2.7V. Selecting diodes with higher or

Figure 6: Simple Diode Regulator Circuit Diagram

lower Vt thresholds would allow for finer tuning of the circuit operation.

Output Voltage Level Translation Solutions

The circuit illustrated in figure 7, utilises a Maxim MAX3370 Level translator circuit to level shift the low voltage output of the DataFlash device to a high voltage output compatible with the 5V CMOS circuit. The MAX3370 is capable of 2Mbps data transfer rates, which should be suitable for the majority of applications. Table 1 provides a short list of semiconductor manufacturers offer-

Figure 7: Example of a Voltage Level Translator

	Function	Manufacturer	Web Site
	Voltage regulation	Linear Technology	www.linear-tech.com
	Voltage regulation	Texas Instrument	www.ti.com
	Voltage regulation	Analog Devices	www.analog.com
	Level Translators	Maxim	www.maxim-ic.com
	Level Translators	Dallas Semiconductor	www.dalsemi.com

Table 1 – A short list of potential Voltage regulator and Level translator, manufacturers.

ing Level translators suitable for this application.

Conclusion

As this application note detailed, Atmel's AT45DBxxxB 3 volt DataFlash family can be easily interfaced to 5-volt devices in new systems or where legacy designs need to be supported. The system designer needs only to account for the proper I/O levels on the output side of the DataFlash device, peak current requirements during erase /programming cycles, and VCC supply voltage demands. The solution to overcome the differences in interface voltages will be determined ultimately by several factors, cost, space, practicality, system specification and performance. The scope of these changes has been minimised by Atmel’s advance consideration of the impact of essential technology migra-

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A T M E L A P P L I C A T I O N S J O U R N A L

Thisis articleti le describesi Atmel’st l’s FingerChipi ip technologyt l forf electronicl t ic fingerprintfi i t sensingi thatt t combinesi

thet advantagest off smallll size,iz , lowl cost,t, highi accuracy,, zeroz maintenance,i t , lowl

energy consumptionti and andportabilityportability. This. Thistech- technologynology has has applicationsli ti inin a widei range off fixedfi and portablet le secured devicesi includingi l i

access controlt l systems,t , cash terminals,t i l , publiclic transport,t t, PCs,, PDAs,, Smartt Card readers and motort vehiclesi l .. ItIt can be used inin almostl t any situationit ti where rapid,i , reliableli le and accuratete identificationi tifi ti or authenticationt ti ti off an individuali i i l isis requiredi ..

FingerChip™ Technology for Biometric Security

Introduction		gerprint is associated with specific electrical and thermal characteristics of the
In today’s world, the need for effective security is evident. Without effective		supporting skin. This means that light, heat or electrical capacitance (or a
security, many everyday activities are compromised. Specific security concerns		combination of these) may be used to capture fingerprint images. A fingerprint
include:		is established during fetal development, it does not change as a person ages,
• Protecting computer systems, PDAs, mobile phones, Internet appliances		and it re-grows to its original pattern after an injury. After reaching adulthood,
and similar devices from unauthorized access or use		a person’s fingerprints remain the same size. Identical twins do not have iden-
• Protecting motor vehicles and other valuable items from unauthorized		tical fingerprints. A small percentage of the population (for example miners or
access or use		musicians) has fingerprints that are permanently disfigured by manual activi-
• Preventing theft and fraud in financial transactions, in particular		ties. In developed countries this proportion is decreasing and does not consti-
electronic transactions including credit card payments and payments via		tute a significant problem for fingerprint-based recognition systems.
the Internet		There are several algorithmic methods for extracting a characteristic template
• Restricting access to workplaces, warehouses and secure areas, such as
military installations, to authorized personnel		from a fingerprint. The most popular methods are based on pattern recognition
• Screening access to public transportation, in particular air travel		or minutiae extraction. In the case of minutiae-based algorithms, a fingerprint
• Authenticating the identity of an individual in drivers’ licenses, health		is characterized by gross features such as arches, loops and whorls, and fine
cards, ID cards, and similar administrative documents.		features (minutiae), principally bifurcations, deltas (Y-shaped junctions) and
		terminations of ridges. Typically, between 30 and 40 minutiae are present in
A major factor in ensuring security is the unique identification of indi-		a fingerprint. Each of these is characterized by its position (co-ordinates), type
viduals, or the authentication that a person is who he or she claims			(bifurcation, delta or termination) and
to be. This must be done reliably, rapidly, non-intrusively and at rea-			orientation. See Figure 1 for an exam-
sonable cost. In the past, this has been done by methods such as			ple. The set of these minutiae charac-
security tokens (passports, badges, etc), secure knowledge (pass-			teristics can provide a template for a
words PIN codes, signature, etc.) or recognition by a guardian (door-			fingerprint. Provided that these charac-
keeper). These traditional approaches are all limited with respect to			teristics	are	measured	sufficiently
the above criteria. A promising approach for the future is biometrics.			accurately, the probability of two dif-
Biometrics offers a convenient, reliable and low-cost means of identi-			ferent fingerprints having				identical
fying or authenticating individuals, and can be implemented in unsu-			templates is extremely low.
pervised and remote situations. Biometrics seeks to identify individu-			Electronic imaging technology and pat-
als uniquely by measuring certain physical and behavioral character-
istics and extracting a sample (also called a sampled template or live			tern recognition algorithms are now
template) from these measurements in a standard data format. This			sufficiently advanced for the template
sample is compared with a template (also called an enrolled template			of a fingerprint to be extracted auto-
or signature), based on the same characteristics, that has been estab-			matically. In many cases standards
lished as the unique identity of that individual and stored in the secu-			exist for the extracted template. These
rity system. A close match between sample and template confirms			standards	are	normally	for	minutia-
	Figure 1: Minutiae of a Typical Fingerprint
the identity of the individual.			based templates, the most notable
		being from the USA National Institute of Standards and Technology (NIST).
Attention has been focused on a small number of physical characteristics that		However, adherence to a standard almost always limits the flexibility of the
can identify individuals uniquely, notably voice, gait, face, iris and retina pat-		algorithm developer, and restricts the use of their proprietary intellectual prop-
terns, palm prints and fingerprints. (DNA is excluded from this list because DNA		erty (IP). Thus there is often a tradeoff between adherence to a standard ver-
sampling is intrusive and slow.) Work is proceeding to develop electronic recog-		sus accuracy and speed when considering standardization.
nition systems based on all of these. This article focuses on fingerprints as the		Fingerprint Sensor Technologies
most advanced, mature and well-developed option. Based on centuries of
experience and extensive research, fingerprints are at present considered to be		A number of different technologies for electronic fingerprint sensing are at pres-
the most reliable biometric for uniquely identifying an individual. In spite of		ent under development. The most widely known are optical, capacitive, radio,
some recent legal challenges in the USA, they are still regarded as giving proof		pressure, micro-electromechanical and thermal. This section outlines each of
of identity beyond reasonable doubt in almost all cases. The majority of the		them and explains Atmel’s choice of thermal as the most promising technolo-
biometric-based security systems in operation today are based on fingerprint		gy for its patented FingerChip™ product.
recognition.		Optical: A variant of a digital camera can be used to capture optical images
Physiologically, a fingerprint is a configuration of ridges that contain individual		of fingerprints. The fingertip is placed on a glass plate, suitably illuminated. A
pores, separated by valleys. These are supported by the underlying structure		lens assembly is required that is adapted to the close proximity of the object.
of blood vessels immediately below the skin. The morphology (shape) of a fin-		The image is captured by a CMOS or CCD image array with a suitable resolu-

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References

1.Common Biometric Exchange File Format (CBEFF), January 2001, USA National Institute of Standards and Technology (NIST), Web http://www.nist.gov

2.FBI Integrated Automated Fingerprint Identification System (IAFIS), USA Federal Bureau of Investigation, Web: http://www.fbi.gov/hq/cjisd/iafis

3.Smart Cards and Biometrics in PrivacySensitive Secure Personal Identification Systems, May 2002, Smart Card Alliance, Web: http://www.smartcardalliance.org/

4.The Biometric Consortium, Web: http://www.biometrics.org

5.International Biometric Industry Association (IBIA), Web: http://www.ibia.org

6.BioAPI Consortium, Web: http://www.bioapi.org

7.London Metropolitan Police, Web: http://www.met.police.uk

8.Ridges and Furrows (Private Web Site), Web: http://www.ridgesandfurrows.homestead.com

A T M E L A P P L I C A T I O N S J O U R N A L

tion, and transformed into a grayscale representation (between two and sixteen shades are generally sufficient). A disadvantage of this technique is the latent print that is left on the sensing plate that can be re-utilized. Another is the difficulty in distinguishing between live fingertips and well-molded imitations.

Capacitive: When a fingertip is placed against an array of charge-sensitive pixels, variations in the dielectric between a ridge (mainly water) and a valley (air) cause the capacitance to vary locally. This enables ridges and valleys to be identified, and an image to be constructed. Despite the vulnerability of this method to electrostatic discharge (ESD) and other parasitic electrical fields, it is one of the most popular techniques for fingerprint image capture. It is, however, relatively easy to deceive with an artificial fingertip or latent print.

Radio: If a fingertip is energized with a low-intensity radio wave, it acts as a transmitter, and the distance variation between ridges and valleys can be detected by an array of suitably tuned antenna pixels. It requires the fingertip to be in contact with the emitting region of the sensor (generally around the periphery). Because it relies on the physiological properties of the skin, it is difficult to deceive a radio sensor with an artificial fingertip. The weak point of this technique is the quality of the contact between the finger and the transmitting ring, which can also become uncomfortably hot.

Pressure: A pressure-sensitive pixel array can be constructed from piezo-elec- tric elements that captures the pattern of ridges in a fingerprint pressed against it. Despite the numerous disadvantages of this technique (low sensitivity, inability to distinguish between real and fake fingertips, susceptibility to damage from excessive pressure, etc.) some companies are pursuing this approach with product prototypes.

Micro-electro-mechanical: Micro-electro-mechanical systems (MEMS) are on the cusp between R&D and deployment in a number of applications. An array of micro-mechanical sensors that detects the ridges and valleys in a fingertip has been constructed in laboratories, but the robustness of such a device is not assured. It would also be impossible to distinguish between a real and an artificial fingertip by this method.

Thermal: Pyro-electric material is able to convert a difference in temperature into a specific voltage. This effect is quite large, and is used in infrared cameras. A thermal fingerprint sensor based on this material measures the temperature differential between the sensor pixels that are in contact with the ridges and those under the valleys, that are not in contact. The thermal approach has numerous benefits. These include strong immunity to electrostatic discharge, and the absence of a signal transmitted to the fingertip. Thermal imaging functions as well in extreme temperature conditions as at room temperature. It is almost impossible to deceive with artificial fingertips. A disadvantage of the thermal technique is that the image disappears quickly. When a finger is placed on the sensor, initially there is a big difference in temperature, and therefore a signal, but after a short period (less than a tenth of a second), the image vanishes because the finger and the pixel array have reached thermal equilibrium. This is one of the reasons for using a scanning technique for image capture, described below.

Static or Scanned Image

Most of the above technologies for image capture can be applied in two different ways. One is to use a static image capture window that is the same size as the required fingerprint image and hold the fingertip against the window for the time interval required to capture the image. This approach has the advantage of capturing an entire image in one operation. Its significant disadvantages include the large die size required (and therefore increased IC cost, see Figure 2), and the fact that a latent print is retained on the image capture win-

dow. The second approach is to use a rectangular window that is the width of the required image and only a few pixels high, and sweep the fingertip vertically over it. This approach requires the image to be scanned in sections and re-constructed by software. Its advantages include a significantly reduced die size (and therefore IC cost), a stable image in the case of thermal capture and the fact that it is self-cleaning. No latent print remains on the image window after a scan. This method is mandatory for thermal image capture due to the short duration of the temperature differential.

Figure 2: Reduced Die Size Decreases IC Unit Cost

Atmel’s Choice: Scanned Thermal Imaging

The combination of thermal image capture and a scanning window gives the benefits of small die size, low unit cost, passive operation, reliable functionality over a wide range of environmental conditions and security against artificial fingertips or the re-use of latent images. These benefits have led Atmel to its choice of scanned thermal imaging for its FingerChip IC.

FingerChip Technology

Atmel’s AT77C101B FingerChip IC for fingerprint image capture combines detection and data conversion circuitry in a single rectangular CMOS die. It captures the image of a fingerprint as the finger is swept vertically over the sensor window. It requires no external heat, light or radio source. (See Figure 3.)

Figure 3: The FingerChip Die Mounted on a Chip-on-Board (COB) Support

The FingerChip Sensor

The FingerChip sensor comprises an array of 8 rows by 280 columns, giving 2240 temperature-sensitive pixels. An additional dummy column is used for calibration and frame identification. The pixel pitch of 50 mm by 50 mm provides a resolution of 500 dpi over an image zone of 0.4 mm by 14 mm. This is adequate to capture a frame of the central portion of a fingerprint at an acceptable image resolution. This resolution also complies with the Image Quality Specification (IQS) from the IAFIS (Integrated Automated Fingerprint Identification System) of the U.S. Federal Bureau of Investigation (FBI). The pixel clock is programmable at up to 2 MHz, giving an output of 1780 frames per second. This is more than adequate for a typical sweeping velocity. An

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A T M E L A P P L I C A T I O N S J O U R N A L

image of the entire fingerprint is re-constructed from successive frames using software provided by Atmel.

FingerChip Functionality

The FingerChip sensor and data conversion circuitry are fabricated on a single monolithic die measuring 1.7 mm by 17.3 mm. The functional elements are shown in Figure 4.

The cycle of operations for each frame is as follows:

1.One column is selected amongst the 280 + 1 in the sensor array. Columns are selected sequentially from left to right with wraparound. After reset, output commences from the leftmost column.

2.Each pixel in the column sends its temperature value as an analog signal to the bank of amplifiers.

3.Two lines at a time are selected (odd and even) to send their amplified analog values to the 4-bit analog-to-digital converters (ADCs). These analog values are also available as outputs (not shown in the functional diagram).

4.The two four-bit digital equivalents are latched and sent in parallel as one byte via the parallel outputs De0-3 (even line) and Do0-3 (odd line).

Figure 5 shows the sequence of outputs for one frame, and Figure 6 shows the succession of frames that are output continuously while the FingerChip is in active mode.

FingerChip Features

FingerChip possesses a number of outstanding features that make it ideally suited for a variety of demanding security applications. In terms of robustness, the IC is naturally protected against electro-static discharges (ESD) up to at least 16 kV. The frame window is resistant to abrasion, being qualified for up to at least one million finger sweeps. It is also able to resist considerable applied pressure.

FingerChip’s operating voltage is 3.3V to 5V, with a power consumption of 20 mW at 3.3V, 1 MHz. This is equivalent to approximately 7 mA on the power

supply pin. It features a nap mode with reset enabled, clock stopped, temperature stabilization disabled and output disabled to put the output lines in highimpedance state. In nap mode, power consumption is limited to leakage current only. In normal operation, the sensor is entirely passive, using the thermal energy in the applied fingertip to obtain its measurements. However, if the temperature differential between the finger and the sensor falls too low (less than one degree) a temperature stabilization feature is activated to slightly raise the temperature of the IC and recover the contrast.

FingerChip Benefits

The benefits of the FingerChip technology derive from its thermal sensing technique, its frame sweeping method of image capture, and the integration of the sensor and data conversion circuitry as a single IC.

The thermal sensing approach requires no signal transmission to the fingertip, making use of the physiological properties of a live fingertip. This reduces its power requirements, and any potential discomfort to the person associated with energizing the fingertip with current or radio waves. The sweeping method of image capture reduces the silicon area required by the sensor array by a factor of 5, leading to a similar reduction in unit cost. The re-constructed image is, however, of a high resolution. It also means that the sensor window is self-cleaning, with no latent prints left after an image capture. If a person is being forced to provide a fingerprint impression, an erratic movement of the fingertip over the window (or a fingertip saturated in sweat) will prevent an image from being obtained. Independent tests have also established that it is difficult to sweep an artificial fingertip smoothly enough to enable an image to be reconstructed.

Integrating the image sensor and conversion circuitry in a single CMOS IC reduces costs and power consumption, and increases operational speed. It also makes it possible to integrate encryption or other application-specific circuitry on the same die or in a stacked die package for enhanced security.

Fingerprint Recognition Systems

Figure 4: FingerChip Functional Diagram

Figure 5: FingerChip Frame Output

Figure 6: FingerChip Frame Sequence

Fingerprint recognition can be used in a wide range of applications, but they all require the same set of basic procedures. These are independent of the technology used for fingerprint sensing, and the software used for template and sample extraction and comparison.

Enrollment and Matching

As an initial step, the fingerprints of the identified population are enrolled. Operationally, fingerprints are captured and compared against the database of enrolled individuals, or a subset of it (in the limit, one single enrolled fingerprint). This process is known as matching.

Enrolment consists in capturing and storing the reference version of the fingerprint of an identified individual. Needless to say, this must take place under secure circumstances, without the possibility of an imposter giving the fingerprint, or of the data obtained being tampered in any way. The fingerprint obtained, or the set of data extracted from it, is known as the template (also called enrolled template) of the individual.

During the operation of the system, for example at the point of entry to a secure building,

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A T M E L A P P L I C A T I O N S J O U R N A L

fingerprints are captured and processed in the same ways as during enrollment. The data obtained, known as a sample (also called sampled template), is compared against the set (or a subset) of templates. If a match is obtained, the individual presenting the sample is identified. (If the sample is compared against a single template, for example to confirm the identify the owner of a Smart Card, the process is known as authentication or validation.) Both enrolment and matching follow the same initial series of data processing steps, as explained below in the context of FingerChip.

Image Acquisition

Image acquisition consists in obtaining a bitmap, at an adequate resolution, of all or part of the fingerprint. The way that this is done by FingerChip is explained in the previous section. The outcome of this step is a sequence of horizontal frames, each 8 x 280 pixels at 4-bit resolution, that together give the complete image of the fingerprint.

Image Reconstruction

Provided that the fingertip has been swept across the sensor window at a reasonable rate, the overlap between successive frames enables an image of the entire fingerprint to be reconstructed. See Figure 7. This is done using software supplied by Atmel as part of the FingerChip deliverable. The reconstructed image is at 8-bit resolution due to resolution enhancement during frame reconstruction. This in compliance with the FBI IQS specification mentioned previously. The reconstructed image is typically 25 mm x 14 mm, equivalent to 500 x 280 pixels. At 8-bit resolution per pixel, this requires 140K bytes of storage per image. Larger or smaller images can be derived from this, using standard image processing techniques, depending on the requirements of the application.

Template or Sample Extraction

For reasons of security, and due to data storage limitations, it is not advisable to store images of entire fingerprints in the fingerprint recognition system. (A reference image may be stored in a secure location during enrolment as a backup and for access in exceptional circumstances, but it is not required for the normal functioning of the system.) The normal procedure is to extract a unique template from the image, using pattern recognition or the principle of minutiae as described before. During enrolment, this gives the enrolled template, and during verification it gives the sampled template. The procedure is identical in both cases.

There are several reasons for this:

-- A typical set of 36 minutiae, each requiring four bytes of storage, occupies only 144 bytes. This is a considerable compression from the file size of the entire image.

-The fingerprint cannot be re-constructed from the template. This reduces the possibility of fraudulent use of the data by electronic intruders or dishonest employees.

-The template can be further compressed by any standard data compression algorithm, and it can also be encrypted if required. This is important for applications such as fingerprint-enhanced Smart Cards, where data storage space is at a premium, and high security is essential.

Template extraction is performed by third-party software, generally following an industry standard procedure for the identification and description of minutiae, and their representation.

Template/Sample Matching

The final stage in the matching procedure is to compare the sampled template with a set of enrolled templates (identification), or a single enrolled template (authentication) if the identity of a single person is being established.

Figure 7: Fingerprint Image Reconstruction

It is highly improbable that the sample is bit-wise identical to the template. This is due to approximations in the scanning procedure (at 50 mm resolution this is far from exact), misalignment of the images and errors or approximations introduced in the process of extracting the minutiae. Accordingly, a matching algorithm is required that tests various orientations of the image and the degree of correspondence of the minutiae, and assigns a numerical score to the match. Above a certain (arbitrary) level, a match is declared.

This gives rise to two possible types of error:

-False Acceptance, where a non-corresponding sample and template give a high enough score to be accepted. This permits an imposter to be accepted by the system. The probability of this occurring is the False Acceptance Rate (FAR).

-False Rejection, where a corresponding sample and template do not produce a high enough score to create a match. This results in an enrolled person being rejected by the system. The probability of this occurring is the

False Rejection Rate (FRR).

The crossover rate is the point where the FAR and FRR rates intersect as a function of the matching score. See Figure 8 (hypothetical FAR/FRR values).

Note: The crossover rate is the point where the curves intersect.

All fingerprint recognition systems attempt to minimize both FAR and FRR, but in practice there is a tradeoff between the two. Reducing the FAR increases the FRR and vice-versa. The cutoff point for acceptance/rejection needs to be adjusted in order to minimize the consequences of the two classes of error. In most cases false acceptance is more serious, because an imposter is admitted

Figure 8: FAR/FRR as a Function of Matching Score

by the system, with all the consequences that entails. The consequences of false rejection can range from annoying to life threatening, depending on the application, in particular whether there is an alternative or manual backup system available. Some systems are sophisticated enough to include an interme-

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