Dueck R.Digital design with CPLD applications and VHDL.2000

340 C H A P T E R 8 • Introduction to Programmable Logic Architectures

All functions must be in SOP form. Outputs for NOT, AND, OR, Exclusive OR, and Exclusive NOR are active HIGH. Therefore, polarity fuses on the outputs for F1, F2, F3, F6, and F7 are blown. NAND and NOR outputs are active LOW; the polarity fuses for F4 and F5 remain intact.

Figure 8.10 shows the logic diagram of the programmed PAL. If only active-LOW outputs were available, we would need to rewrite some of the equations to make the outputs correspond to their DeMorgan equivalent forms, as follows:

AND: F2 B C

OR: F3 D E

XOR: F6 K L K L K L

XNOR: F7 M N M N M N

FIGURE 8.10

Programmed Logic Diagram for Seven Logic Functions

8.4 • PAL Devices With Registered Outputs

341

8.4 PAL Devices With Registered Outputs

K E Y T E R M S

Register A digital circuit such as a flip-flop or array of flip-flops that stores one or more bits of digital information.

Registered output An output of a programmable array logic (PAL) device having a flip-flop (usually D-type) that stores the output state.

Flip-flops are generally found in programmable logic devices as registered outputs. A register is one or more flip-flops used to store data. Registered outputs in programmable array logic (PAL) devices can be used for the same functions as individual flip-flops.

Figure 8.11 shows the logic diagram of a PAL device with eight registered outputs: a PAL16R8. The fuse matrix is identical to that of a PAL16L8 device; the differences

FIGURE 8.11

PAL16R8 Logic Diagram

342 C H A P T E R 8 • Introduction to Programmable Logic Architectures

	between the two devices are the registered outputs, a dedicated clock input (pin 1), and a
	pin for enabling all registered outputs (pin 11).
	With Registered PAL, the number of outputs shown in the part number indicates the
	number of registered outputs. For example, a PAL16R4 device has four registered outputs
	and four combinational I/O pins, a PAL16R6 device has six registered outputs and two
	combinational I/O pins, and a PAL16R8 has eight registered outputs.
EXAMPLE 8.2	A common data operation is that of “rotation.” Figure 8.12 illustrates how a 4-bit number
	can be rotated to the right by 0, 1, 2, or 3 places by a circuit called a “barrel shifter.”
	To rotate the data, move all bits the required number of places to the right. As data reach
	the rightmost position, move them to the beginning so that they are transferred in a
	closed loop.
FIGURE 8.12
Example 8.2
Rotation to the Right (4-bit Data)

This operation is usually performed by serially shifting the data the required number of places and feeding back the last output to the first input of a serial shift register.

Rotation can also be accomplished by a parallel transfer operation. We can load the bits of the input into four D flip-flops in the order determined by two select inputs, S1 and S0. Assume that the binary number S1 S0 is the same as the rotation number in Figure 8.12. Table 8.1 summarizes the contents of the circuit after one clock pulse is applied.

Table 8.1 Rotation to the Right by a Selectable Number of Bits

S1	S0	QA	QB	QC	QD	Rotation
0	0	A	B	C	D	0
0	1	D	A	B	C	1
1	0	C	D	A	B	2
1	1	B	C	D	A	3

Sketch a circuit, using gates and flip-flops, that can accomplish this rotation as a parallel transfer function. Briefly explain its operation.

Write the Boolean expression(s) for the circuit.

Show how the circuit can be implemented by a PAL16R4 device by drawing fuses on its logic diagram.

SOLUTION Figure 8.13 shows a parallel transfer circuit (barrel shifter) that will perform the specified rotation. The circuit works by enabling one AND gate in each group of four for each combination of S1 and S0. For example, when S1 S0 00, the rotation is 0 and the leftmost AND gate of each group is enabled, transferring the parallel data into the flip-flops so that DA A, DB B, DC C, and DD D. After one clock pulse, QA

QB QC QD ABCD.

8.4 • PAL Devices With Registered Outputs

343

FIGURE 8.13

Example 8.2

Rotation by Parallel Transfer (Barrel Shifter)

Similarly, if S1 S0 10, we select a rotation of 2. The third AND gate from the left is selected in each group of four. This makes the data DA C, DB D, DC A, and DD B appear at the flip-flop inputs. After one clock pulse, QA QB QC QD CDAB.

The same principle governs the circuit operation for the other two select codes. The Boolean equations for the circuit are:

QA S1 S0 A S1 S0 D S1 S0 C S1 S0 B

QB S1 S0 B S1 S0 A S1 S0 D S1 S0 C

QC S1 S0 C S1 S0 B S1 S0 A S1 S0 D

QD S1 S0 D S1 S0 C S1 S0 B S1 S0 A

344 C H A P T E R 8 • Introduction to Programmable Logic Architectures

FIGURE 8.14

Example 8.2

Programmed PLD for Selectable Bit Rotation

These equations imply that each registered output requires us to use four product lines,

one for each product term. The programmed logic diagram is shown in Figure 8.14.

8.5 • Universal PAL and Generic Array Logic (GAL)

345

8.5 Universal PAL and Generic Array Logic (GAL)

K E Y T E R M S

One-time programmable (OTP) A property of some PLDs that allows them to be programmed, but not erased.

Generic array logic (GAL) A type of programmable logic device whose outputs can be configured as combinational or registered and whose programming matrix is based on electrically erasable logic cells.

Universal PAL A PLD based on erasable cells and configurable outputs, much like GAL, but primarily designed to emulate PAL devices, such as PAL16L8.

Output logic macrocell (OLMC) An input/output circuit that can be programmed for a variety of input or output configurations, such as active HIGH or active LOW, combinational or registered. Often just called a macrocell.

In-system programmability (ISP) The ability of a PLD to be programmed through a standard four-wire interface while installed in a circuit.

JTAG port A four-wire interface specified by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit.

Architecture cell A programmable cell that, in combination with other architecture cells, sets the configuration of a macrocell.

Global architecture cell An architecture cell that affects the configuration of all macrocells in a device.

Local architecture cell An architecture cell that affects the configuration of one macrocell only.

Global clock A clock signal in a PLD that clocks all registered outputs in the device.

There are several limitations of standard low-density PALs. First, these devices are one-time programmable (OTP). Since the AND matrix of a PAL is programmable by blowing metal fuse links, programming is permanent; there is no opportunity to correct or update a design. In development of a new design, where many modifications must be made to the original design, this can be particularly wasteful. Second, standard PAL outputs are permanently configured either as combinational or registered. A given PAL has a certain number of each type of output, which may not be optimum for the design. Third, a standard PAL cannot be programmed while it is installed in a circuit.

A number of low-density PLDs have been developed to address these concerns. Devices such as the PALCE16V8 Universal PAL (Vantis Corporation), and the GAL16V8 and GAL22V10 Generic Array Logic (Lattice Semiconductor)* are based on sum-of-products fuse matrices, just as the earlier-version PALs. However, these devices are based on electrically erasable read only memory (EEPROM or E2PROM) cells, rather than fuses, which allow them to be erased and reprogrammed about 10,000 times. A programmed device will hold its data for about 20 years.

Universal PALs and GALs also have programmable input/output configurations. An I/O pin can be configured as a registered output, a combinational output, or a dedicated input, as required. Additionally, an output can be specified as active-HIGH or active-LOW.

*Vantis has recently been acquired by Lattice, so these devices are really produced by the same company

346 C H A P T E R 8 • Introduction to Programmable Logic Architectures

Devices such as the ispGAL22V10 or the Altera MAX7000S series can be programmed while installed in a circuit via a standard four-wire interface called a JTAG port.

This property is known as in-system programmability (ISP).

PALCE16V8

Figure 8.15 shows one I/O pin and its associated circuitry for a PALCE16V8 Universal PAL. (The “V” stands for “variable” or “versatile” architecture.) It consists of a programmable SOP array with 8 product terms and an output logic macrocell (OLMC), or just “macrocell”, which determines the I/O configuration for that pin. The various configuration options are selected by a network of four multiplexers that are programmed by a set of architecture cells that set the MUX select inputs HIGH or LOW.

24 27 28 31

CLK OE

Select eighth
product term				1	1
1 1				1	0
			VCC	0	0
0 X				0	1
1 0
	SL03	Select registered or
		combinational output
				1	1
	SG1
				0 X
		D	Q	1	0
Select active	SL13		Q
high or low				1 0
		Select input or		1 1
				0 X
		feedback type	SG1

FIGURE 8.15

Output Logic Macrocell for a PALCE16V8 PLD

Select output enable term

15 I/O3

SL03

A global architecture cell, SG1, selects configuration options for all macrocells in the device. Two local configuration cells, SL0n and SL1n, select configurations for I/On only. (In this case, the cells shown are SL03 and SL13 for configuration of I/O3.)

Figure 8.16 shows the different macrocell configurations for a PALCE16V8 Universal PAL. Most of these configurations are designed to emulate an I/O of a standard PAL, so that an old-style PAL can be replaced by a Universal PAL, and can be programmed by data for the older PAL. The macrocells can also be configured in a pattern that does not conform to an older device.

Figure 8.17 shows the logic diagram of a PALCE16V8 Universal PAL. The device has eight dedicated inputs, eight macrocells, a Clock pin and an Output Enable pin. The latter two signals are shown in the macrocell diagram of Figure 8.15 as the lines labeled CLK and OE.

If there are registered outputs, the clock input (pin 1) provides a global clock function. That is, all registered outputs are clocked simultaneously by this signal. (Some other PLDs provide an option to clock a registered output from a product term in the AND matrix, allowing several clock functions in one chip.) If there are no registered outputs used in the PLD, pin 1 can be used as an input.

8.5 • Universal PAL and Generic Array Logic (GAL)

347

OE		OE

	D Q		D Q
CLK	Q	CLK	Q

a. Registered active low

b. Registered active high

c. Combinatorial I/O active low					d. Combinatorial I/O active high
			VCC					VCC

Note 1			Note 1

e. Combinatorial output active low

Notes:

1.Feedback is not available on pins 15 and 16 in the combinatorial output mode.

2.This configuration is not available on pins 15 and 16.

FIGURE 8.16

f. Combinatorial output active high

Adjacent I/O pin Note 2

g. Dedicated input

Macrocell Configurations for a PALCE16V8 PLD (Courtesy of Lattice Semiconductor Corporation)

Pin 11 provides an active-LOW Output Enable function. This is selected by local architecture cells to provide control of the output tristate buffer, either from the OE pin or from a product term in theAND matrix. If the OE function is unused, the pin can be used as an input.

GAL22V10

Figure 8.18 shows the logic diagram of a GAL22V10 generic array logic device. This industry-standard device has a number of features that make it superior to the PALCE16V8.

348	C H A P T E R				8	• Introduction to Programmable Logic Architectures
	0	3	4	7	8	11 12	15 16	19 20	23 24	27 28	31
CLK/I0	1
														1 1		20	VCC
											1 1		VCC	1 0
														0 0
											0 X			0 1
											1 0
	0											SL07		1 0
												SG1		0 X		19	I/O7
												D	Q	1 0
	7											SL17	Q
I1														1 0
	2													1	1
														0 X
													SG0			SL07
														1	1
											1	1	VCC	1	0
														0 0
											0 X			0 1
											1	0
	8											SL06		1 0
												SG1		0 X		18		I/O6
												D	Q	1	0
	15											SL16	Q
														1 0
I2
	3													1	1
														0 X
													SG1			SL06
														1 1
											1 1		VCC	1 0
														0 0
											0 X			0 1
											1 0
	16											SL05		1 0
												SG1		0 X		17		I/O5
													Q
												D		1 0
	23											SL15	Q
														1 0
I3
	4													1	1
														0 X
													SG1			SL05
														1 1
											1 1		VCC	1 0
														0 0
											0 X			0 1
											1 0
	24											SL04		1 0
												SG1		0 X				16	I/O4
												D	Q	1 0
	31											SL14	Q
														1 0
I4
	5													1	1
														0 X		SL04
	0	3	4	7	8	11 12	15 16	19 20	23 24	27 28	31	CLK OE	SG1

FIGURE 8.17 (a)

PALCE16V8 Logic Diagram (Courtesy of Lattice Semiconductor Corporation)

8.5 • Universal PAL and Generic Array Logic (GAL)

349

		0	3	4	7	8	11 12	15 16	19 20	23 24	27 28	31	CLK OE
															1	1
												1	1	VCC	1	0
															0	0
												0 X			0	1
												1	0
32													SL03		1 0
													SG1		0 X
																15	I/O3
													D	Q
															1 0
39													SL13	Q
I5															1	0
	6														1	1
															0 X
														SG1		SL03
															1	1
												1 1		VCC	1	0
															0	0
												0 X			0	1
												1 0
40													SL02		1	0
													SG1		0 X
																14	I/O2
													D	Q	1
																0
47													SL12	Q
															1	0
I6
	7														1	1
															0 X
														SG1		SL02
															1	1
												1 1		VCC	1	0
															0	0
												0 X			0	1
												1 0
48													SL01		1 0
													SG1		0 X
														Q		13	I/O1
													D
															1 0
55													SL11	Q
															1	0
I7
	8														1	1
															0 X
														SG1		SL01
															1	1
												1 1		VCC	1	0
															0	0
												0 X			0	1
												1 0
56													SL00		1 0
													SG1		0 X
																12	I/O0
													D	Q	1
																0
63													SL10	Q
															1	0
I8
	9														1	1
															0 X
GND	10	0	3	4	7	8	11 12	15 16	19 20	23 24	27 28	31		SG0		SL00
																13	OE/19

FIGURE 8.17 (b)

(PALCE16V8 Logic Diagram