Philips Semiconductors |
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Product specification |
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48 × 84 pixels matrix LCD controller/driver |
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PCD8544 |
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12 |
AC CHARACTERISTICS |
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SYMBOL |
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PARAMETER |
CONDITIONS |
MIN. |
TYP. |
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MAX. |
UNIT |
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fOSC |
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oscillator frequency |
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20 |
34 |
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65 |
kHz |
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fclk(ext) |
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external clock frequency |
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10 |
32 |
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100 |
kHz |
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fframe |
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frame frequency |
fOSC or fclk(ext) = 32 kHz; note 1 |
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67 |
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Hz |
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tVHRL |
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VDD to |
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LOW |
Fig.16 |
0(2) |
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30 |
ms |
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RES |
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tWL(RES) |
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LOW pulse width |
Fig.16 |
100 |
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ns |
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RES |
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Serial bus timing characteristics |
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fSCLK |
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clock frequency |
VDD = 3.0 V ±10% |
0 |
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4.00 |
MHz |
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Tcy |
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clock cycle SCLK |
All signal timing is based on |
250 |
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ns |
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tWH1 |
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SCLK pulse width HIGH |
20% to 80% of VDD and |
100 |
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ns |
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maximum rise and fall times of |
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tWL1 |
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SCLK pulse width LOW |
100 |
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ns |
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10 ns |
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tsu2 |
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set-up time |
60 |
− |
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ns |
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SCE |
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th2 |
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hold time |
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100 |
− |
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ns |
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SCE |
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tWH2 |
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min. HIGH time |
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100 |
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ns |
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SCE |
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th5 |
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start hold time; note 3 |
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100 |
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ns |
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SCE |
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tsu3 |
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− |
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− |
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D/C |
set-up time |
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100 |
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ns |
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th3 |
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− |
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− |
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D/C |
hold time |
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100 |
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ns |
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tsu4 |
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SDIN set-up time |
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100 |
− |
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− |
ns |
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th4 |
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SDIN hold time |
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100 |
− |
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− |
ns |
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Notes |
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1. |
T |
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= |
fclk ( ext) |
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frame |
------------------- |
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480 |
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2.RES may be LOW before VDD goes HIGH.
3.th5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE (see Fig.15).
1999 Apr 12 |
20 |
Philips Semiconductors |
Product specification |
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48 × 84 pixels matrix LCD controller/driver |
PCD8544 |
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12.1Serial interface
tsu2 |
th2 |
tWH2 |
SCE |
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tsu3 |
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th3 |
th5 |
th5 |
D/C |
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tWL1 |
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tsu2 |
tWH1 |
Tcy |
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SCLK |
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tsu4 |
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th4 |
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SDIN |
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MGL644 |
Fig.15 Serial interface timing.
12.2Reset
handbook, full pagewidthVDD
tWL(RES) 
tRW 
RES
MGL645
Fig.16 Reset timing.
1999 Apr 12 |
21 |