7. Read the text and find the answers to the following questions:

1. What is referred to as a subscalar CPU?

2. Why are subscalar CPUs considered inefficient?

3. What techniques are used to achieve scalar and better performance?

4. What is instruction pipelining?

5. What are the benefits of superscalar processors?

Parallelism

The CPUs which can operate on and execute only one instruction at a time are referred to as subscalar. They are considered inefficient as the entire CPU must wait for that instruction to complete before proceeding to the next instruction. As a result the subscalar CPU gets “hung up” on instructions which take more than one clock cycle to complete execution.

Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave less linearly and more in parallel*. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques*. Instruction level parallelism (ILP) seeks to increase the rate at which instructions are executed within a CPU, and thread level parallelism (TLP) purposes to increase the number of threads (effectively individual programs) that a CPU can execute simultaneously.

One of the simplest methods to use parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is the simplest form of a technique known as instruction pipelining, and is utilized in almost all modern general-purpose CPUs. Pipelining allows more than one instruction to be executed at any given time by breaking down the execution pathway into discrete stages*. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and retired.

Further improvement upon the idea of instruction pipelining led to the development of a method that decreases the idle time of CPU components even further. Designs that are said to be superscalar include a long instruction pipeline and multiple identical execution units. In a superscalar pipeline, multiple instructions are read and passed to a dispatcher, deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for every instruction. Graphics processors and computers with SIMD (single instruction, multiple data) and MIMD (multiple instructions, multiple data) features often provide ALUs that can perform arithmetic on vectors and matrices.

8. Give English equivalents for the following.

Плавающая точка, независимо от, последовательность шагов, программный счетчик, квадратный корень, запрашивать операцию, уменьшать время простоя, улучшать производительность, конвейерная обработка инструкций, предшествующий.

9. Fill in the gaps with the appropriate words.

1. The fundamental operation of most CPUs is to ------- a sequence of stored instructions called a program.

a) control b) examine c) execute

2. The first step in CPU operation is ------ an instruction from program memory.

a) retrieving b) sending c) changing

3. The instruction decoder ------- software instructions.

a) performs b) interprets c) seeks

4. The ALU performs the actual arithmetic operations, namely, addition, subtraction, multiplication, ------.

a) decision b) division c) definition

5. The CPUs which can execute only one instruction at a time are referred to as ------.

a) scalar b) superscalar c) subscalar

6. ILP seeks to ------ the rate at which instructions are executed within a CPU.

a) improve b) decrease c) increase

7. One of the ways to use parallelism is to begin the first steps of instruction fetching and decoding ------ the prior instruction finishes executing.

a) after b) before c)until