ABOUT THIS MANUAL
1.5.RELATED LITERATURE
The following books contain additional material related to Intel processors:
•Intel Pentium® Pro Processor Specification Update, Order Number 242689.
•Intel Pentium® Processor Specification Update, Order Number 242480.
•AP-485, Intel Processor Identification and the CPUID Instruction, Order Number 241618.
•AP-578, Software and Hardware Considerations for FPU Exception Handlers for Intel Architecture Processors, Order Number 242415-001.
•Pentium® Pro Processor Family Developer’s Manual, Volume 1: Spec ifications, Order Number 242690-001.
•Pentium® Processor Family Developer’s Manual, Order Number 241428.
•
•
•
•
•
Intel486™ Microprocessor Data Book, Order Number 240440.
Intel486™ SX CPU/Intel487™ SX Math Coprocessor Data Book , Order Number 240950.
Intel486™ DX2 Microprocessor Data Book , Order Number 241245.
Intel486™ Microprocessor Product Brief Book , Order Number 240459.
Intel386™ Processor Hardware Reference Manual , Order Number 231732.
•Intel386™ Processor System Software Writer's Guide , Order Number 231499.
•Intel386™ High-Performance 32-Bit CHMOS Microprocessor with Integrated Memory Management, Order Number 231630.
•376 Embedded Processor Programmer's Reference Manual, Order Number 240314.
•80387 DX User's Manual Programmer's Reference, Order Number 231917.
•376 High-Performance 32-Bit Embedded Processor, Order Number 240182.
•Intel386™ SX Microprocessor , Order Number 240187.
•Microprocessor and Peripheral Handbook (Vol. 1), Order Number 230843.
•AP-528, Optimizations for Intel's 32-Bit Processors, Order Number 242816-001.
1-8
2
Instruction Format
CHAPTER 2
INSTRUCTION FORMAT
This chapter describes the instruction format for all Intel Architecture processors.
2.1.GENERAL INSTRUCTION FORMAT
All Intel Architecture instruction encodings are subsets of the general instruction format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), one or two primary opcode bytes, an addressing-form specifier (if required) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base) byte, a displacement (if required), and an immediate data field (if required).
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Instruction |
|
Opcode |
|
|
ModR/M |
|
|
SIB |
|
Displacement |
Immediate |
|
||||||||
|
Prefixes |
|
|
|
|
|
|
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
Up to four |
1 or 2 byte |
|
|
1 byte |
|
|
1 byte |
|
Address |
Immediate |
|
|||||||||
|
prefixes of |
opcode |
(if required) |
|
(if required) |
displacement |
data of |
|
|||||||||||||
|
1-byte each |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
of 1, 2, or 4 |
1, 2, or 4 |
|
|||
|
(optional) |
|
|
|
|
|
|
|
|
|
|
|
|
|
bytes or none |
bytes or none |
|
||||
|
7 |
|
6 5 |
|
3 2 |
0 |
|
7 |
6 5 |
|
3 2 |
0 |
|
|
|
||||||
|
|
|
Mod |
|
Reg/ |
|
|
R/M |
|
|
Scale |
Index |
|
|
Base |
|
|
|
|||
|
|
|
|
Opcode |
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Figure 2-1. Intel Architecture Instruction Format
2.2.INSTRUCTION PREFIXES
The instruction prefixes are divided into four groups, each with a set of allowable prefix codes:
•Lock and repeat prefixes.
—F0H—LOCK prefix.
—F2H—REPNE/REPNZ prefix (used only with string instructions).
—F3H—REP prefix (used only with string instructions).
—F3H—REPE/REPZ prefix (used only with string instructions).
•Segment override.
—2EH—CS segment override prefix.
—36H—SS segment override prefix.
2-1