ARM PrimeCell DMA Controller (PL080) Signal Descriptions

A.5 AHB master bus request signals

Table A-5 describes the AHB master bus request signals.

				Table A-5 AHB master bus request signal descriptions
	Name	Type	Source/	Description
			destination
	HBUSREQDMACM1	Output	Arbiter	Bus request signal used by the PrimeCell DMA controller to
				request the AHB bus.
	HBUSREQDMACM2	Output	Arbiter	Bus request signal used by the PrimeCell DMA controller to
				request the AHB bus.
	HGRANTDMACM1	Input	Arbiter	This signal is used to indicate that the DMA master is selected.
				The master gains bus ownership when HGRANTDMAC and
				HREADY are HIGH on the rising edge of HCLK.
	HGRANTDMACM2	Input	Arbiter	This signal is used to indicate that the DMA master is selected.
				The master gains bus ownership when HGRANTDMAC and
				HREADY are HIGH on the rising edge of HCLK.

A-8

Copyright © 2000, 2001 ARM Limited. All rights reserved.

ARM DDI 0196C

ARM PrimeCell DMA Controller (PL080) Signal Descriptions

A.6 Scan test control signals

Table A-6 describes the internal scan test control signals.

Table A-6 Internal scan test control signal descriptions

	Name	Type	Source/	Description
			destination
	SCANENABLE	Input	Scan controller	Scan enable.
	SCANINHCLK	Input	Scan controller	Scan data input for HCLK domain.
	SCANOUTHCLK	Output	Scan controller	Scan data output for HCLK domain.

ARM DDI 0196C

Copyright © 2000, 2001 ARM Limited. All rights reserved.

A-9

ARM PrimeCell DMA Controller (PL080) Signal Descriptions

A-10

Copyright © 2000, 2001 ARM Limited. All rights reserved.

ARM DDI 0196C