- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Timing diagram conventions
- •Further reading
- •ARM publications
- •Other publications
- •Feedback
- •Feedback on this document
- •Feedback on the ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050)
- •1 Introduction
- •1.1 About the ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050)
- •1.1.1 Features of the PrimeCell KMI
- •1.2 AMBA compatibility
- •2 Functional Overview
- •2.1 ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) overview
- •2.2 PrimeCell KMI functional description
- •2.2.1 AMBA APB interface and register block
- •2.2.2 Transmit block
- •2.2.3 Receive block
- •2.2.4 Controller block
- •2.2.5 Timer/clock divider blocks
- •2.2.6 Synchronization logic
- •2.2.7 Test registers and logic
- •2.3 PrimeCell KMI operation
- •2.3.1 Interface reset
- •2.3.2 Clock signals
- •2.3.3 Keyboard clock and data signals
- •2.3.4 Keyboard/mouse data output
- •2.3.5 Keyboard data input
- •2.3.6 Timing requirements
- •3 Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Summary of PrimeCell KMI registers
- •3.3 Register descriptions
- •3.3.1 KMICR: [6] (+ 0x00)
- •3.3.3 KMIDATA: [8] (+ 0x08)
- •3.3.4 KMICLKDIV: [4] (+ 0x0C)
- •3.3.5 KMIIR: [2] (+ 0x10)
- •3.4 Interrupts
- •3.4.1 Interrupt generation logic
- •4 Programmer’s Model for Test
- •4.1 PrimeCell KMI test harness overview
- •4.2 Scan testing
- •4.3 Test registers
- •4.3.2 KMITCR [5] (+0x80)
- •4.3.3 KMITMR [4] (+0x84)
- •4.3.4 KMITISR [2] (+0x88)
- •4.3.5 KMITOCR [3] (+0x8c)
- •4.3.6 KMISTG1 [6] (+0x90)
- •4.3.7 KMISTG2 [5] (+0x94)
- •4.3.8 KMISTG3 [8] (+0x98)
- •4.3.9 KMISTATE [4] (+0x9c)
- •A.1 AMBA APB signals
- •A.2 On-chip signals
- •A.3 Signals to pads
Introduction
1.1About the ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050)
The PrimeCell PS2 Keyboard/Mouse Interface (KMI) is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip peripheral that is developed, tested and licensed by ARM.
The PrimeCell KMI is an AMBA slave module, and connects to the Advanced Peripheral Bus (APB). The PrimeCell KMI can be used to implement a keyboard or mouse interface that is IBM PS2 or AT compatible.
Figure 1-1 illustrates the connections to the PrimeCell KMI.
AMBA |
AMBA |
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APB |
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|
APB |
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|
|
|
|
|
interface |
|
KMIINTR |
|
KMIDATAIN |
KMIRXINTR |
|
KMIDATA |
|
|
|
KMITXINTR |
PrimeCell |
nKMIDATAEN |
|
||
|
KMI |
|
|
core |
|
KMIREFCLK |
logic |
KMICLKIN |
|
|
|
nKMIRST |
|
KMICLK |
|
|
|
SCANMODE |
|
nKMICLKEN |
|
|
|
|
|
Open drain |
|
PrimeCell KMI block |
bidirectional |
|
|
input/output cells |
|
Figure 1-1 Connections to the PrimeCell KMI |
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© Copyright ARM Limited 1999. All rights reserved. |
DDI 0143C |
Introduction
1.1.1Features of the PrimeCell KMI
The PrimeCell KMI has the following features:
•compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into System-on-a-Chip (SoC) implementation
•IBM PS2 or AT-compatible keyboard or mouse interface
•half-duplex bidirectional synchronous serial interface using open-drain outputs for clock and data
•programmable 4-bit reference clock divider
•operation in polled or interrupt-driven mode
•separately maskable transmit and receive interrupts
•single combined interrupt output
•odd parity generation and checking
•register bits for override of keyboard clock and data lines.
Additional test registers and modes are implemented for functional verification and manufacturing test.
DDI 0143C |
© Copyright ARM Limited 1999. All rights reserved. |
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