Programmer’s Model

3.6Interrupts

A single, maskable, active HIGH interrupt RTCINTR is generated by the PrimeCell RTC when a match occurs between the counter and the equivalent match value:

•This interrupt is enabled or disabled by changing the mask bit in RTCIMSC. To enable the interrupt, set bit 0 HIGH.

•The status of the interrupt mask can be read from bit[0] of RTCMIS.

•Writing 1 to bit[0] of RTCICR clears the RTCINTR flag.

•The RTC interrupt, RTCINTR, is output through an output pin.

ARM DDI 0224B

Copyright © 2001 ARM Limited. All rights reserved.

3-13

Programmer’s Model

3-14

Copyright © 2001 ARM Limited. All rights reserved.

ARM DDI 0224B