Ballistic gate MOSFET

A MOSFET equivalent circuit is shown, including the parasitic draingate and gate-source capacitors. In a transformer isolated power converter, the leakage inductance of the transformer is significant, and, for very fast switching, the load current can be considered to be constant.

Overcoming the Miller effect:

The MOSFET is a three terminal device, so the gate current must equal the sum of the drain current and the source current. The drain current is from an inductive load, so for very fast MOSFET switching, the drain current can be considered to be a constant.

The "Miller current" is a current through the drain-source capacitance, and it has as its upper limit the drain current. If the gate current exceeds the drain current, there is insufficient current available through the drain-gate capacitance to maintain the feed-back component of the Miller effect, and

Adding a capacitor from the drain to the source of the MOSFET has a very beneficial effect on the Miller current. Remembering that the drain current is the upper limit of the Miller current, and remembering that the drain current is held constant by the inductive nature of the load, consider now that the load current has two parallel paths in which to flow, one being the drain-gate capacitance and the other being the parallel capacitor.

The load current thus divides between the capacitors. If one assumes equal capacitances, for discussion, the current divides equally, and the Miller current now has a new upper limit, half what it was before. (The drainsource channel is a third defined current path, but as the MOSFET begins to turn off, its impedance rises. To the extent that it continues to conduct, the upper limit of the Miller current is further reduced.)

The Miller current being half, the gate voltage can be pulled down more quickly. Also, with twice the total capacitance, the drain-source voltage will rise more slowly. With a very low impedance gate drive, the MOSFET may be able to pinch off before the drain voltage has risen much at all, virtually eliminating cross over power.

The parallel capacitor will discharge into the MOSFET upon turn on, however, increasing losses, unless zero-volt turn on can be used.

Ballistic turn on.

The energy of the drain-source capacitance and the parallel capacitor can be recovered and used for the gate drive in the circuit shown above. Consider that the MOSFET is off, so the turn off MOSFET is clamping the gate to the source. To begin the turn on sequence, the turn on MOSFET is turned on, still keeping the turn off MOSFET turned on. Current will begin to flow from the drain through the inductor to the gate lead, which is shunted to the source.

This will begin to discharge the drain-gate capacitance, causing a Miller current tending to make the gate negative. However, it is clamped to the source, so the gate-source voltage remains nearly zero. Once the drain voltage is low, the off MOSFET is turned off, and the energy stored in the inductor as current will flow very quickly into the gate. (It may be desirable to provide a clamp means to limit the gate voltage).

This technique can be adapted to other circuits. The source of the gate drive voltage could be a static voltage source, or it could be the "other" MOSFET drain in a 100% duty cycle push pull circuit.

Small parallel MOSFET:

Another way to mitigate the Miller effect is to use two MOSFETs in parallel, one much larger than the other, shown pictorially by their different size in the sketch above. The MOSFETs could be separate parts, but preferably they are sections of the same die. Each has a gate, labeled "on", and each has a gate pull down driver MOSFET, the gates of which are labeled "off".

The turn off sequence begins by turning off the larger MOSFET while leaving the smaller one on. The load current will transfer to the smaller MOSFET, and the collective drain voltage will rise somewhat, as it has a higher Rds-on, but it will be too small to put a significant dv/dt on the drainsource capacitance of the larger MOSFET. With no significant dv/dt, there will be no significant Miller current, and the gate of the larger MOSFET can be pulled low and clamped.

The smaller MOSFET has to handle the entire load briefly so it must have sufficient peak power capability, but the time will be so short that the net power is low. Once the gate of the larger MOSFET is clamped low, the smaller MOSFET is turned off. There will now be a Miller current into both MOSFETs, but it will divide as their respective capacitances. The gate of the larger MOSFET need only be clamped sufficiently so that it does not turn on by the dv/dt, and the gate drive of the smaller MOSFET needs to handle only a fraction of the Miller current that would have been seen if a single large MOSFET was turned off in the usual way.

MOSFET Lead Impedance:

Ld

Lg R g

Q 1

Ls

Commercially available MOSFETs for power converter applications are not well suited for very fast, high current gate drive. The lead and package inductances are much too high, as is the gate resistance. Of particular concern is the gate mesh resistance. Not only does it limit the gate current, it also forms a distributed RC-RC-RC circuit to the various cells of the MOSFET, and there can be significant delay to the cells that are most remote from the gate terminations. Some MOSFETs have a metalized gate net, but most are polycrystalline.

The gate drive too must have very low impedance, both a low resistance and a low inductance.

To implement a very fast gate drive with gate current that is large compared to the drain current, a new MOSFET packaging arrangement is necessary. The gate net resistance can be managed by making a large number of gate connection points widely distributed over the MOSFET die so that the distance through any part of the gate net is short, and the resistance is massively paralleled. A good arrangement would be to have a large number of gate driver cells integrated into the MOSFET, with very short local connections to the gate connection points and to the source metalization.

Low impedance connections:

The first sketch shows gate driver chips immediately proximate to a MOSFET die with a large number of interconnections to groups of cells and the source metalization.

The second sketch shows a gate driver chip mounted on a MOSFET die, and connected to a large number of gate connection points through solder bumps, ball grid or the like.

The third sketch shows various components of a gate drive mounted on the MOSFET die, with a large number of gate connections.

Lastly, the gate drive can be integrated into the MOSFET die, with a large number of gate drive gates distributed over the MOSFET die.

Propagation delay is important, and it should be minimized, but the more critical consideration is the rapid discharge of the gate capacitance.