EIA-364-109 standard.Loop inductance measurement test procedure for electrical connectors

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Figure B.3 – Fifty ohm load reference trace

Figure B.4 – Transmission reference trace

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B.2 Test board reference traces

Test boards shall include reference traces for measuring the frequency domain characteristics of the fixture in order to correct for fixture effects (e.g., discontinuities in impedance). Recommended test fixture configurations include:

B.2.1 A reference trace ending in a via which is shorted to the return path conductor(s). The length of this reference trace should be the same as that of the trace connected to the near end of the specimen.

B.2.2 A reference trace ending in a via which is open with respect to the return path conductor(s). The length of this reference trace should be the same as that of the trace connected to the near end of the specimen.

B.2.3 A reference trace terminated in the specimen environment impedance. The length of this reference trace should be the same as that of the trace connected to the near end of the specimen.

B.2.4 A reference structure consisting of a through transmission trace whose length is equal to the total fixture trace length for a single path, (length of the near end and far end traces). The test fixture shall provide an identical coaxial cable or probe connection at both ends.

NOTE 1 This reference structure should be designed with the same configuration in which the specimen would be used in a typical application (such as footprint pads, grounds, traces, vias, etc).

NOTE 2 The calibration structures above are described as terminating in a via. This is appropriate for pin-in-hole terminations, but is not appropriate for all terminations, e.g. surface mount connectors. Ideally the reference trace should terminate in the same type of pad or connection as the actual connector would experience.

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C Printed circuit board design considerations for electronics measurements (informative)

This annex provides a general overview of circuit board design considerations for numerous electronics measurements, not just inductance. Although several clauses do not pertain to inductance measurements, the information is provided for the user who may design a single test board to perform multiple electronics measurements.

C.1 The designer should take precautions in designing printed-circuit boards for high-speed testing for several reasons. These include reflections due to impedance mismatches, signal attenuation due to skin effect of the narrow conductors, resonance effects due to long traces, crosstalk between traces, and others. Printed circuit board features that may be of concern include vias, SMT pads, probe interface, etc. Electrical discontinuities caused by these features are unavoidable in the test fixture(s), and shall not be overlooked as they may affect the impedance results of the specimen. This annex can not in the space allotted cover these topics in detail, but will attempt to lay the groundwork for further analysis and design, and refer the reader to more detailed treatments of the subject. There are a number of excellent references on the subject, which are listed at the end of this annex.

C.2 When the printed circuit board traces approach critical lengths (defined later in the document), it becomes essential to design the traces to match the impedance of the test equipment to avoid inaccurate results due to reflections. Controlling the line impedance of printed circuit board traces is difficult without the use of embedded reference planes in the board. The preferred reference plane is one connected to signal ground, but any low impedance reference will work (including a voltage plane) if it is sufficiently decoupled. The signal line impedance is determined by conductor geometry, including the trace width and thickness, distance from the ground or other reference plane or conductor, and the dielectric constant of the board material. In the case of differential trace pairs, the spacing between the two traces is also critical. Several formulas exist for calculation of printed circuit board trace impedance, and a number of impedance calculation software tools are also available. The choice of board impedance formula is based on the conductors’ relative placement as well as their position in the board cross-section, some common examples of which are shown in the figures below.

t	w			w
				Ground
	Dielectric	h	b	t
				h
Ground
				Ground
				Dielectric
	(a)			(b)

Figure C.1 - Microstrip (a) and stripline (b) geometries

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C.2.1 In figure C.1 (a), a cross section of a microstrip transmission line is shown. The signal line of width w and thickness t lies on top of the surface of the dielectric layer with relative dielectric constant εr (typically between 4 and 5 for glass-epoxy boards) at a height of h above a ground or other reference plane. The characteristic impedance of a signal line with such a structure is given by the following equation. 1)

Z0	=		87		5.98h
		εr	+1.41	ln
					0.8w +t

C.2.2 This value is approximate, in that it assumes that the conductor is surrounded on three sides by air; if the conductor is covered by solder mask or other material (as is typical), the higher dielectric constant of that material will lower the impedance from the value calculated using the equation.

C.2.3 The stripline structure shown in figure C.1 (b) is one in which the signal line is surrounded by the dielectric material, with ground or reference planes on two sides. The characteristic impedance for the stripline structure is given by the following equation. 2)

			60				4b
Z		=			ln
	0		ε					+	t
				r			0.67πω 0.8
									w

C.2.4 A similar structure also exists where the conductor in question is inside the surface of the printed circuit board but is only adjacent to a ground or reference plane in one direction. This is referred to variously as “buried” microstrip or “covered” microstrip, and is shown in figure C.2.

w

b t

h

Ground

Dielectric

Figure C.2 - Buried microstrip geometry

1)Blood, William R., Jr.: MECL System Design Handbook (Phoenix, AZ: Motorola Semiconductor Products, Inc., 1988), p. 45.

2)Op. cit., p. 48.

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C.2.4.1 The characteristic impedance for this configuration is given by the following

equation. 3)
Z		=	60		5.98h
	0		εr	ln
					0.8w +t

C.2.5 The equations above have all dealt with single-ended (unbalanced) signal lines. In the case of differential (balanced) signals, the impedance is more difficult to compute than the conventional single-ended impedance; the use of field solver software is often necessary to solve this type of problem. The use of vias is to be discouraged where possible, as the capacitance of vias causes impedance mismatches and consequent reflections in the signal path. In the event that surface ground planes are used to construct stripline structures, the surface and buried ground planes should be connected together by vias spaced no more than λ/8 apart, to prevent resonances and other undesired effects on the printed circuit board. Typically, the value for λis the highest frequency at which measurements are to be taken.

C.2.6 Attenuation of high frequency signals (or higher order harmonics of non-sinusoidal signals) due to the so-called skin effect is a well-known phenomenon. Skin effect becomes significant when the skin depth δis less than approximately one third of the conductor thickness. 4) For example, the

skin depth in meters for copper at a given frequency of interest is given by δ = 0.0660 / f 5), or

approximately 2.1 μm at 1 GHz. Assuming 0.035 mm or 35 micrometers (0.0014 inch (1.4 mils)) thick, (commonly referred to as “one ounce” copper) conductors typically used for printed circuit board trace, this would indicate that skin effect would be significant at frequencies above approximately 30 MHz.

3)Buchanan, James E.: BiCMOS/CMOS Systems Design (New York: McGraw-Hill, 1991), op. cit., p. 109.

4)Deutsch, A.: “Electrical Characteristics of Interconnections for High-Performance Systems,” Proceedings of the IEEE, vol. 86, no. 2, February, 1998.

5)Ramo, S., Whinnery, J. R., and Van Duzer, T.: Fields and Waves in Communications Electronics (New York: Wiley, 1969), p.289.

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C.2.7 Another effect that should be considered is resonance. Resonance can cause unexpected results, and even oscillations in the device/fixture. This effect is not just manifested at the frequencies of the exciting signals, but also at harmonics of those frequencies present in the exciting signal; the spectral content of square or nearly square pulses can extend far beyond the expected maximum frequency. The maximum frequency of significant spectral content can be estimated as fmax = 1/πtr, where tr is the rise or fall time of the exciting signal. 6)

NOTE This is independent of the period of the signal. So, for a 100 MHz signal with a rise time of 1 ns, significant spectral energy exists in that signal up to approximately 300 MHz. The “critical length” at which a printed circuit board trace may cause problems due to resonance effects is given by the following equation. 7)

lcrit = tr 2t pd

where:

tr is the rise time of the signal and tpd is the propagation delay in the medium (in the typical case, glass-epoxy). This propagation delay is typically 80-100 ps/cm (200-250 ps/in.) on inside planes of printed circuit boards, and 55 ps/cm (170 ps/in.) on outside planes, resulting in a critical length of approximately 6 cm (2 in.) for a signal rise time of 1 ns.

C.2.8 The length to be used for calculating resonance is the wavelength λ of the frequency of interest in the medium, which is given by the following equation.

λ = vf

where:

ν is the velocity in the medium and ƒ is the frequency of interest. The velocity in the medium is the reciprocal of the propagation delay, or approximately (1-2)x1010 cm/s (4-8x109 in./s), resulting in a wavelength of approximately 50 cm (20 in.) at 300 MHz.

6)Ott, Henry W.: Noise Reduction Techniques in Electronic Systems (NewYork: Wiley, 1976), p. 111.

7)Buchanan, op. cit., p. 125.

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C.2.9 Crosstalk should be considered in the printed circuit board design, most obviously when designing a fixture for measurement of crosstalk, but also for others. The amount of crosstalk introduced is dependent on conductor geometry (width, spacing, and height above ground) as well as the coupling length, so it is difficult to give specific guidance. The reader is referred to 8) for a discussion of the subject. A rule of thumb is that conductor spacing should be three times the conductor width to minimize crosstalk.

C.2.10 Attention shall also be paid to the trace delay, especially when designing fixtures for measurement of propagation delay. Where trace length shall be added to equalize delay between paths on the fixture, sharp corners and serpentine wiring are not to be used. Sharp corners and serpentine wiring introduce impedance mismatches into the paths, and serpentine wiring changes the propagation delay per unit length due to the coupling between adjacent legs of the pattern. This will cause actual delays that are difficult to quantify.

8) Ibid., pp. 114-122.

Other excellent references on these subjects include:

Johnson, H. and Graham, M.: High-Speed Digital Design, a Handbook of Black Magic (Upper Saddle River, NJ: Prentice-Hall, 1993)

Matick, R. E.: Transmission Lines for Digital and Communications Networks (Piscataway, NJ: IEEE Press, 1995)

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D. Mutual inductance coupling coefficient test procedure

(informative)

In addition to the loop inductance measurement, described in the above procedure, and the self and mutual inductance parameters that were referenced, another inductance related parameter is the mutual inductance coupling coefficient. The mutual inductance coupling coefficient is essentially the coupling (or crosstalk) between two current loops due to the magnetic fields created by the currents in both loops. The test method for mutual inductance coupling coefficient is included here.

D.1 Set the vector network analyzer to measure S12 for mutual inductance.

D.2 Calibrate the equipment and fixture according to the manufacturer’s specifications using the calibration standard. The calibration plane should be directly at the probe tip interface to the fixture.

NOTE Due to the low inductance value being measured, it is

recommended that microprobes be used.

D.3 Unless otherwise specified in the referencing document it is recommended that the following

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equipment settings be used:

linear magnitude format,

set network analyzer to display inductance values,

minimum of 401 measurement points,

frequency span – conduct both wideband and narrowband sweeps,

no smoothing,

averaging set to 16 or higher.

NOTE “Wideband” sweep is typically the full range of the network analyzer and “narrowband” sweep is over a limited range (for example 100 MHz wide).

D.4 Fixture measurement

Position the microprobe tips to touch the interface pads of the fixture inductance calibration trace. Measure and record the inductance of the fixture from the chart at the frequency(s) of interest.

NOTE — If specified in the referencing document, an inductance vs. frequency graph may be generated through the use of data acquisition software and spreadsheet software.

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D.5 Specimen measurement

D.5.1 Connect the microprobe attached to port 1 of the vector network analyzer to the first fixture interface pad. Connect the microprobe attached to port 2 of the vector network analyzer to the second fixture interface pad, with the specimen installed, as shown in figure D.1. This arrangement will allow measurement of the loop inductance between the two pads to which the probes are connected. (The microprobe plus specimen installation should be such that it terminates the far end of the driven lines in an electrical short circuit to the return conductor(s). The short circuit may be achieved by using a copper block to minimize any additional inductance.)

D.5.2 Place the specimen a minimum of 5 cm from any object that may introduce error into the measurement.

D.5.3 Measure and record the S12 values over the specified test frequency range or discrete frequencies.

NOTE — If specified in the referencing document, an inductance vs. frequency graph may be generated through the use of data acquisition software and spreadsheet software.

D.5.4 Calculate the mutual inductance coupling coefficient Km using the following equation:

	Km =	{3.98 | S12 |}
		{ f	L}

where:

f = test measurement frequency L = measured loop inductance

NOTE The preceding equation was derived from circuit analysis by looking at the time domain differential equations for a simplified, first order effect two terminal electrical short circuit.

D.6 If requested, repeat D.5 through D.5.4 on multiple lines throughout the specimen.

D.7 When additional measurements with different test frequencies or ranges are required perform the calibration step defined in D.4, then repeat D.5 through D.6 as necessary.