Recommended serial interface for transceiver control V1.0a

Serial Interface for Transceiver Control

Infrared Data Association

RECOMMENDED SERIAL INTERFACE

FOR TRANSCEIVER CONTROL

Version 1.0a

March 29, 2000

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Serial Interface for Transceiver Control

Author:

Franco Iacobelli (National Semiconductor Corporation)

Significant Contributors:

John Petrilla, Takashi Hidai (Agilent Technologies Inc.)

Bryn Owen, Patrick Kam (IBM Corporation)

Ray Chock (Calibre Inc.)

Revision:

March 8, 2000 Table 3-1

Add Rohm to the manufacturers table with ID number OAh.

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Serial Interface for Transceiver Control

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Serial Interface for Transceiver Control

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Serial Interface for Transceiver Control

1.1 OVERVIEW

This document describes a simple serial interface that allows an infrared controller to communicate with one or more infrared transceivers. This interface requires three signals: a clock line that is used for timing, and two unidirectional lines multiplexed with the transmitter (write) and receiver (read) infrared signal lines. The main features of the serial interface are listed below.

-Message Based

-Low Power Consumption

-High Speed

-Simple Protocol

-Bus protocol implemented in hardware or in software through bit banging.

-Read and write capability

-Open Architecture (not patented)

-Easily Expandable

1.2 BASIC CONFIGURATIONS

There are two basic system configurations using the serial interface. The first one is found in portable computers and most embedded systems. In this case two optical transceivers are typically used; one in the front and one in the rear of the system’s chassis. Furthermore, the infrared controller and transceivers are in close proximity of one another. The interconnections are usually implemented with single ended signals since their contribution to EMI is minimal. Handling multiple optical transceivers is easily accomplished by assigning them different addresses. The second configuration exists typically in desktop systems. In this case only one transceiver is required. The transceiver is usually mounted on a tiny PC board and communicates with the infrared controller through a shielded cable approximately 1.5 m long. This PC board and cable assembly is commonly referred to as Infrared Dongle. Currently existing Dongles use single ended signaling. However, due to the inherent EMI problems of this arrangement, there is a strong incentive in future Dongles to use differential signaling.

			OFE A
		IRTX/SWDAT	TX/SWDAT
		IRRX/SRDAT
	Infrared		RX/SRDAT	Optical
		SCLK
	Controller		SCLK	Transceiver
		GND	A_SL
		VCC

OFE B

TX/SWDAT
RX/SRDAT	Optical
SCLK	Transceiver
VCC A_SL

Figures 1-1 and 1-2 below show two typical transceiver configurations.

Figure 1-1. Interface to Two Infrared Transceivers.

The data lines are multiplexed with the transmitter and receiver signals and a different address for each transceiver can be selected.

The pullup resistor on the IRRX/SRDAT line is used to prevent spurious low-going transitions during the time in which both transceivers are disabled. When no infrared communication is in progress and the serial interface is

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Serial Interface for Transceiver Control

idle, the IRTX/SWDAT line is kept low and IRRX/SRDAT is kept high.

	Connector	Shielded Cable		LVDS
	VCC		VCC	Transceiver
	GND		GND
	IRTX+/SWDAT+				TX/SWDAT
	IRTX-/SWDAT-
Infrared	IRRX+/SRDAT+				RX/SRDAT	Optical
Controller	IRRX-/SRDAT-
	SCLK+					Transceiver
	SCLK-				SCLK
				GND	A_SL

Figure 1-2. Infrared Dongle with Differential Signaling.

1.3 FUNCTIONAL DESCRIPTION

The serial interface is designed to interconnect two or more devices. One of the devices is always in control of the serial interface and is responsible for starting every transaction. This device functions as the bus master and is always the infrared controller. The infrared transceivers act as bus slaves and only respond to transactions initiated by the master. A bus transaction is made up of one or two phases. The first phase is the Command Phase and is present in every transaction. The second phase is the Response Phase and is present only in those transactions in which data must be returned from the slave. If the operation involves a data transfer from the slave, there will be a Response Phase following the Command Phase in which the slave will output the data.

The start bit of the slave response, if present, must occur 4 clock cycles after the last bit of the Command Phase, as shown in figures 1-8 and 1-9, otherwise it is assumed that there will be no response. The master must always complete the transaction normally. More precisely, it must not stop the clock and terminate the transaction earlier if the slave does not respond.

The SCLK line is always driven by the master and is used to clock the data being written to or read from the slave. This line is driven by a totem-pole output buffer. The SCLK line is always stopped when the serial interface is idle to minimize power consumption and to avoid any interference with the analog circuitry inside the slave. There are no gaps between the bytes in either the Command or Response Phase. Each byte of data in both Command and Response Phases is preceded by one start bit. Data is always transferred in Little Endian order (least significant bit first). Input data is sampled on the rising edge of SCLK. Output data from the controller is clocked by SCLK falling edge. Output data from the slave is clocked by SCLK rising edge. This makes the interface signaling less sensitive to timing skews. Figure 1-3 shows the interface timing including the data sampling points.

The data to be written to the slave is carried on the IRTX/SWDAT line. When the control interface is idle, this line carries the infrared data signal used to drive the transmitter LED. When the first low-to-high transition on SCLK is detected at the beginning of the command sequence, the slave will disable the transmitter LED. The infrared controller then outputs the command string on the IRTX/SWDAT line. On the last SCLK cycle of the command sequence the slave re-enables the transmitter LED and normal infrared transmission can resume. No transition on SCLK must occur until the next command sequence, otherwise the slave will disable the transmitter LED again. Read data is carried on the IRRX/SRDAT line. The slave disables the internal signal from the receiver photo diode during the response phase of a read transaction. The addressed slave will output the read data on the IRRX/SRDAT line regardless of the setting of the Receiver Output Enable bit in the Mode Selection register 0. Non addressed slaves will tri-state the IRRX/SRDAT line. When the transceiver is powered up, the IRTX/SWDAT line should be kept low and SCLK should be cycled at least 30 times by the infrared controller before the first command is issued on the IRTX/SWDAT line. This guarantees that the transceiver interface circuitry will properly initialize and be ready to receive commands from the controller (note 1). In case of a multiple transceiver configuration, only one transceiver should have the receiver output enabled. If these transceivers are connected to the infrared controller via short traces (like in a notebook computer), a series resistor (approx. 200 ohms) should be placed on the receiver output from each transceiver to prevent large currents in case a conflict occurs due to a programming error.

Note 1: Since there is no reset line, the serial interface can be initialized by implementing a self-resetting interface state machine in the transceiver. This machine must be guaranteed to

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Serial Interface for Transceiver Control

transition to the idle state by cycling the SCLK line at least 30 times while keeping IRTX low.

It is only from the idle state that the transceiver state machine can correctly accept a command from the infrared controller.

Figures 1-4 to 1-9 show the waveforms for the various serial interface operations.

CLOCK SIGNAL

GENERATED BY THE

INFRARED CONTROLLER

CLOCK SIGNAL

RECEIVED BY THE

INFRARED TRANSCEIVER

WRITE DATA

OUTPUT BY THE

INFRARED CONTROLLER

WRITE DATA

SAMPLED BY THE

INFRARED TRANSCEIVER

READ DATA

OUTPUT BY THE

INFRARED TRANSCEIVER

READ DATA

SAMPLED BY THE

INFRARED CONTROLLER

Figure 1-3. Serial Interface Timing.

This figure shows the signal delays due to the cable as well as the data sampling points for both the infrared controller and transceiver.

30 CLOCK CYCLES

SCLK

IRTX/

SWDAT

IRRX/

SRDAT

TLED_DIS

(INTERNAL SIGNAL)

Figure 1-4. Initial Reset Timing

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Serial Interface for Transceiver Control

START

ADDRESS & CONTROL

SCLK

IRTX/

SWDAT

IRRX/

SRDA

TLED_DIS

(INTERNAL SIGNAL)

RES

(INTERNAL SIGNAL)

Figure 1-5. Special Command Waveform

START	ADDRESS, INDEX, DIR.	START	DATA
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
TLED_DIS
(INTERNAL SIGNAL)
RES
(INTERNAL SIGNAL)

Figure 1-6. Write Data Waveform.

Note 2: If the APEN bit in control register 0 is set to 1, the internal signal from the receiver photo diode is disconnected and the IRRX/SRDAT line from the addressed transceiver is pulsed low for one clock cycle at the end of a write or special command. No pulse is generated if a broadcast address is used.

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Serial Interface for Transceiver Control

START	ADDRESS, DIR.	START	EXT. INDEX	START	DATA
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
TLED_DIS
(INTERNAL SIGNAL)
RES
(INTERNAL SIGNAL)

Figure 1-7. Write Data Waveform with Extended Index.

START	ADDRESS, INDEX, DIR.	START	DATA
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
RX_EN
(INTERNAL SIGNAL)
RX_DIS
(INTERNAL SIGNAL)
TLED_DIS
(INTERNAL SIGNAL)
RES
(INTERNAL SIGNAL)

Figure 1-8. Read Data Waveform.

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Serial Interface for Transceiver Control

START	ADDRESS, DIR.	START	EXT. INDEX	START	DATA
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
RX_EN
(INTERNAL SIGNAL)
RX_DIS
(INTERNAL SIGNAL)
TLED_DIS
(INTERNAL SIGNAL)
RES
(INTERNAL SIGNAL)

Figure 1-9. Read Data Waveform with Extended Index.

Note 3: During a read transaction the infrared controller sets the IRTX/SWDAT line low for one clock cycle after sending the address and index byte (or bytes). It will then set it high and low again three clock cycles before the end of the transaction.

It is strongly recommended that optical transceivers monitor this line

instead of counting clock cycles in order to detect the end of the read transaction.

This will always guarantee correct operation in case two or more transceivers from different manufacturers are sharing the serial interface.

2.0 BUS PROTOCOL

A set of commands is provided to handle the various transactions between the master and each of the slaves. The set is fully expandable to handle future requirements. The general command format is shown in figure 2-1. Data is transferred in little endian order, bit 0 of byte 0 is the first bit transferred, bit 7 of byte 2 is the last.

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ADDR INDX

BYTE 0

0

C

7	0	7		0
DATA or E_INDX				DATA
	BYTE 1			BYTE 2

Figure 2-1. General Command Format.

The first byte, common to all transactions, contains the address of the slave to be accessed and two control fields. The first control field is the INDX field. It determines whether the transaction is a Special Transaction or a Data Transaction. The second control field (C field) consists of only one bit and either determines the data transfer direction or it further qualifies a special transaction. The second byte is present in read and write transactions.

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