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XC95144XV High-Performance

CPLD

DS051 (v2.8) April 15, 2005

Features

•144 macrocells with 3,200 usable gates

•Available in small footprint packages

-100-pin TQFP (81 user I/O pins)

-144-pin TQFP (117 user I/O pins)

-144-pin CSP (117 user I/O pins)

•Optimized for high-performance 2.5V systems

-Low power operation

-Multi-voltage operation

•Advanced system features

-In-system programmable

-Two separate output banks

-Superior pin-locking and routability with Fast CONNECT™ II switch matrix

-Extra wide 54-input Function Blocks

-Up to 90 product-terms per macrocell with individual product-term allocation

-Local clock inversion with three global and one product-term clocks

-Individual output enable per output pin

-Input hysteresis on all user and boundary-scan pin inputs

-Bus-hold ciruitry on all user pin inputs

-Full IEEE Standard 1149.1 boundary-scan (JTAG)

•Fast concurrent programming

•Slew rate control on individual outputs

•Enhanced data security features

•Excellent quality and reliability

-20 year data retention

-ESD protection exceeding 2,000V

Description

The XC95144XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns.

Power Estimation

Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.

Product Specification

For a general estimate of ICC, the following equation may be used:

PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO

Separating internal and I/O power here is convenient because XC9500XV CPLDs also separate the corresponding power pins. PIO is a strong function of the load capaci-

tance driven, so it is handled by I = CVf. ICCINT is another situation that reflects the actual design considered and the

internal switching speeds. An estimation expression for ICCINT (taken from simulation) is:

ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG

where:

MCHS = # macrocells used in high speed mode MCLP = #macrocells used in low power mode

PTHS = average p-terms used per high speed macrocell PTLP = average p-terms used over low power macrocell fMAX = max clocking frequency in the device

MCTOG = % macrocells toggling on each clock (12% is frequently a good estimate

This calculation was derived from laboratory measurements of an XC9500XV part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx application note XAPP361, “Planning for High Speed

XC9500XV Designs.”

Typical ICC (mA)

250

200

150

100

50

Performance

High

Power

Low

221 MHz

120 MHz

0

40

80

120

160

200

Clock Frequency (MHz)

DS051_01_121501

Figure 1: Typical ICC vs. Frequency for XC95144XV

© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Product Specification	1-800-255-7778

XC95144XV High-Performance CPLD

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			3
	JTAG Port	1	JTAG	In-System Programming Controller
			Controller

			54
		18	Function
I/O			Block 1
I/O			Macrocells
			1 to 18
I/O	Matrix
		18	Block 2
I/O			54
			Function
	Switch
I/O			1 to 18
			Macrocells
Blocks	II
I/O	CONNECT		54
I/O		18	Function
			Block 3
I/O	Fast		Macrocells
I/O			1 to 18
3
I/O/GCK			54
1		18	Function
I/O/GSR			Block 4
4			Macrocells
I/O/GTS			1 to 18
			54
		18	Function
			Block 8
			Macrocells
			1 to 18
			DS051_02_041000

Figure 2: XC95144XV Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

Supported I/O Standards

Table 1: IOSTANDARD Options

IOSTANDARD	VCCIO
LVTTL	3.3V
LVCMOS2	2.5V
X25TO18	1.8V

The XC95144XV CPLD features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS2 standard is used in 2.5V applications.

XC9500XV CPLDs are also 1.8V I/O compatible. The X25TO18 setting is provided for generating 1.8V compatible outputs from a CPLD normally operating in a 2.5V environ-

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		Product	Specification

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XC95144XV High-Performance CPLD

ment. The ISE software automatically groups outputs with

matching IOSTANDARD settings into the same VCCIO bank when no location constraints are specified. The default I/O

Standard for pads without IOSTANDARD attributes is LVTTL for XC9500XV devices.

Absolute Maximum Ratings

Symbol	Description	Value	Units
VCC	Supply voltage relative to GND	–0.5 to 2.7	V
VCCIO	Supply voltage for output drivers	–0.5 to 3.6	V
V	Input voltage relative to GND(1)	–0.5 to 3.6	V
IN
V	Voltage applied to 3-state output(1)	–0.5 to 3.6	V
TS
TSTG	Storage temperature (ambient)	–65 to +150	oC
TJ	Junction temperature	+150	oC

Notes:

1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +3.6V, provided this overor undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

2.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

3.For solder specifications, see Xilinx Packaging.

Recommended Operation Conditions

Symbol		Parameter		Min	Max	Units
V	CCINT	Supply voltage for internal logic	Commercial T = 0oC to +70oC	2.37	2.62	V
		and input buffers	A
			Industrial T = –40oC to +85oC	2.37	2.62
			A
VCCIO		Supply voltage for output drivers for 3.3V operation		3.0	3.6	V
		Supply voltage for output drivers for 2.5V operation		2.37	2.62	V
		Supply voltage for output drivers for 1.8V operation		1.71	1.89	V
	VIL	Low-level input voltage		0	0.8	V
	VIH	High-level input voltage		1.7	3.6	V
	VO	Output voltage		0	VCCIO	V

Quality and Reliability Characteristics

Symbol	Parameter	Min	Max	Units
TDR	Data retention	20	-	Years
NPE	Program/Erase cycles (endurance)	1,000	-	Cycles
VESD	Electrostatic Discharge (ESD)	2,000	-	Volts

DS051 (v2.8) April 15, 2005

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Product Specification

XC95144XV High-Performance CPLD

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DC Characteristics (Over Recommended Operating Conditions)

Symbol	Parameter	Test Conditions	Min	Max	Units
VOH	Output high voltage for 3.3V outputs	IOH = –4.0 mA	2.4	-	V
	Output high voltage for 2.5V outputs	IOH = –1.0 mA	2.0	-	V
	Output high voltage for 1.8V outputs	IOH = –100 A	90% VCCIO	-	V
VOL	Output low voltage for 3.3V outputs	IOL = 8.0 mA	-	0.4	V
	Output low voltage for 2.5V outputs	IOL = 1.0 mA	-	0.4	V
	Output low voltage for 1.8V outputs	IOL = 100 A	-	0.4	V
IIL	Input leakage current	VCC = 2.62V	-	±10	A
		VCCIO = 3.6V
		VIN = GND or 3.6V
IIH	Input high-Z leakage current	VCC = 2.62V	-	±10	A
		VCCIO = 3.6V
		VIN = GND or 3.6V
		VCC min < VIN < 3.6V	-	±150	A
CIN	I/O capacitance	VIN = GND	-	10	pF
		f = 1.0 MHz
ICC	Operating Supply Current	VI = GND, No load	29		mA
	(low power mode, active)	f = 1.0 MHz

AC Characteristics

		XC95144XV-5		XC95144XV-7
Symbol	Parameter					Units
		Min	Max	Min	Max
TPD	I/O to output valid	-	5.0	-	7.5	ns
TSU	I/O setup time before GCK	3.5	-	4.8	-	ns
TH	I/O hold time after GCK	0	-	0	-	ns
TCO	GCK to output valid	-	3.5	-	4.5	ns
fSYSTEM	Multiple FB internal operating frequency	-	222.2	-	125.0	MHz
TPSU	I/O setup time before p-term clock input	1.0	-	1.6	-	ns
TPH	I/O hold time after p-term clock input	2.5	-	3.2	-	ns
TPCO	P-term clock output valid	-	6.0	-	7.7	ns
TOE	GTS to output valid	-	4.0	-	5.0	ns
TOD	GTS to output disable	-	4.0	-	5.0	ns
TPOE	Product term OE to output enabled	-	7.0	-	9.5	ns
TPOD	Product term OE to output disabled	-	7.0	-	9.5	ns
TAO	GSR to output valid	-	10.0	-	12.0	ns
TPAO	P-term S/R to output valid	-	10.7	-	12.6	ns
TWLH	GCK pulse width (High or Low)	2.2	-	4.0	-	ns
TPLH	P-term clock pulse width (High or Low)	5.0	-	6.5	-	ns
TAPRPW	Asynchronous preset/reset pulse width (High or Low)	5.0	-	6.5	-	ns

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