ATtiny2313A/4313

Table 10-10. Overriding Signals for Alternate Functions in PD3..PD0

	Signal	PD3/INT1/	PD2/INT0/XCK/CKOUT/	PD1/TXD/
	Name	PCINT14	PCINT13	PCINT12	PD0/RXD/PCINT11
	PUOE	0	0	TXD_OE	RXD_OE
	PUOV	0	0	0	PORTD0 •
						PUD
	DDOE	0	0	TXD_OE	RXD_EN
	DDOV	0	0	1	0
	PVOE	0	XCKO_PVOE	TXD_OE	0
	PVOV	0	XCKO_PVOV	TXD_PVOV	0
	PTOE	0	0	0	0
	DIEOE	INT1 Enable +	INT0 Enable/	PCINT12	PCINT11
		PCINT14	XCK Input Enable/PCINT13
	DIEOV	PCINT14	PCINT13	PCINT12	PCINT11
	DI	INT1 Input/	INT0 Input/XCK Input/	PCINT12	RXD Input/PCINT11
		PCINT14	PCINT13
	AIO	–	–	–	–

10.3Register Description

10.3.1MCUCR – MCU Control Register

Bit		7	6	5	4	3	2	1	0
0x35 (0x55)		PUD	SM1	SE	SM0	ISC11	ISC10	ISC01	ISC00	MCUCR
Read/Write		R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value		0	0	0	0	0	0	0	0

• Bit 7 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 56 for more details about this feature.

10.3.2PORTA – Port A Data Register

Bit		7	6	5	4	3	2	1	0
0x1B (0x3B)		–	–	–	–	–	PORTA2	PORTA1	PORTA0	PORTA
Read/Write		R	R	R	R	R	R/W	R/W	R/W
Initial Value		0	0	0	0	0	0	0	0

10.3.3DDRA – Port A Data Direction Register

Bit	7	6	5	4	3	2	1	0
0x1A (0x3A)	–	–	–	–	–	DDA2	DDA1	DDA0	DDRA
Read/Write	R	R	R	R	R	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

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10.3.4PINA – Port A Input Pins Address

Bit	7	6	5	4	3	2	1	0
0x19 (0x39)	–	–	–	–	–	PINA2	PINA1	PINA0	PINA
Read/Write	R	R	R	R	R	R/W	R/W	R/W
Initial Value	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A

10.3.5PORTB – Port B Data Register

Bit	7	6	5	4	3	2	1	0
0x18 (0x38)	PORTB7	PORTB6	PORTB5	PORTB4	PORTB3	PORTB2	PORTB1	PORTB0	PORTB
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

10.3.6DDRB – Port B Data Direction Register

Bit	7	6	5	4	3	2	1	0
0x17 (0x37)	DDB7	DDB6	DDB5	DDB4	DDB3	DDB2	DDB1	DDB0	DDRB
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

10.3.7PINB – Port B Input Pins Address

Bit	7	6	5	4	3	2	1	0
0x16 (0x36)	PINB7	PINB6	PINB5	PINB4	PINB3	PINB2	PINB1	PINB0	PINB
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A

10.3.8PORTD – Port D Data Register

Bit	7	6	5	4	3	2	1	0
0x12 (0x32)	–	PORTD6	PORTD5	PORTD4	PORTD3	PORTD2	PORTD1	PORTD0	PORTD
Read/Write	R	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

10.3.9DDRD – Port D Data Direction Register

Bit	7	6	5	4	3	2	1	0
0x11 (0x31)	–	DDD6	DDD5	DDD4	DDD3	DDD2	DDD1	DDD0	DDRD
Read/Write	R	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

10.3.10PIND – Port D Input Pins Address

Bit	7	6	5	4	3	2	1	0
0x10 (0x30)	–	PIND6	PIND5	PIND4	PIND3	PIND2	PIND1	PIND0	PIND
Read/Write	R	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A

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