ATtiny2313A/4313
2. See section “Calibration Byte” for more information.
20.3.1Calibration Byte
The signature area of the ATtiny2313A/4313 contains two bytes of calibration data for the internal oscillator. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 8.0 MHz operation. During reset, this byte is automatically written into the OSCCAL register to ensure correct frequency of the oscillator.
There is a separate calibration byte for the internal oscillator in 4.0 MHz mode of operation but this data is not loaded automatically. The hardware always loads the 8.0 MHz calibration data during reset. To use separate calibration data for the oscillator in 4.0 MHz mode the OSCCAL register must be updated by firmware. The calibration data for 4.0 MHz operation is located in the high byte at address 0x01 of the signature area.
20.3.2Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
For the ATtiny2313A the signature bytes are:
1.0x000: 0x1E (indicates manufactured by Atmel).
2.0x001: 0x91 (indicates 2KB Flash memory).
3.0x002: 0x0A (indicates ATtiny2313A device when 0x001 is 0x91).
For the ATtiny4313 the signature bytes are:
1.0x000: 0x1E (indicates manufactured by Atmel).
2.0x001: 0x92 (indicates 4KB Flash memory).
3.0x002: 0x0D (indicates ATtiny4313 device when 0x001 is 0x92).
20.4Reading Lock Bits, Fuse Bits and Signature Data from Software
Fuse and lock bits can be read by device firmware. Programmed fuse and lock bits read zero. unprogrammed as one. See “Lock Bits” on page 178 and “Fuse Bits” on page 179.
In addition, firmware can also read data from the device signature imprint table. See “Device Signature Imprint Table” on page 180.
20.4.1Lock Bit Read
Lock bit values are returned in the destination register after an LPM instruction has been issued within three CPU cycles after RFLB and SPMEN bits have been set in SPMCSR (see page 176). The RFLB and SPMEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles. When RFLB and SPMEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
1.Load the Z-pointer with 0x0001.
2.Set RFLB and SPMEN bits in SPMCSR.
3.Issue an LPM instruction within three clock cycles.
4.Read the lock bits from the LPM destination register.
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If successful, the contents of the destination register are as follows.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Rd |
– |
– |
– |
– |
– |
– |
LB2 |
LB1 |
|
|
|
|
|
|
|
|
|
See section “Parallel Programming” on page 184 for more information.
20.4.2Fuse Bit Read
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits, only the addresses are different.
To read the Fuse Low Byte (FLB), follow the below procedure:
1.Load the Z-pointer with 0x0000.
2.Set RFLB and SPMEN bits in SPMCSR.
3.Issue an LPM instruction within three clock cycles.
4.Read the FLB from the LPM destination register.
If successful, the contents of the destination register are as follows.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Rd |
FLB7 |
FLB6 |
FLB5 |
FLB4 |
FLB3 |
FLB2 |
FLB1 |
FLB0 |
|
|
|
|
|
|
|
|
|
Refer to Table 20-5 on page 180 for a detailed description and mapping of the Fuse Low Byte.
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Rd |
FHB7 |
FHB6 |
FHB5 |
FHB4 |
FHB3 |
FHB2 |
FHB1 |
FHB0 |
|
|
|
|
|
|
|
|
|
Refer to Table 20-4 on page 179 for detailed description and mapping of the Fuse High Byte.
To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure. If successful, the contents of the destination register are as follows.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Rd |
FEB7 |
FEB6 |
FEB5 |
FEB4 |
FEB3 |
FEB2 |
FEB1 |
FEB0 |
|
|
|
|
|
|
|
|
|
Refer to Table 20-3 on page 179 for detailed description and mapping of the Fuse Extended
Byte.
20.4.3Device Signature Imprint Table Read
To read the contents of the device signature imprint table, follow the below procedure:
1.Load the Z-pointer with the table index.
2.Set RSIG and SPMEN bits in SPMCSR.
3.Issue an LPM instruction within three clock cycles.
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ATtiny2313A/4313
4.Wait three clock cycles for SPMEN bits to be cleared.
5.Read table data from the LPM destination register.
If successful, the contents of the destination register are as described in section “Device Signature Imprint Table” on page 180.
The RSIG and SPMEN bits will auto-clear after three CPU cycles. When RSIG and SPMEN are cleared, LPM will work as described in the “AVR Instruction Set” description.
See program example below.
Assembly Code Example
DSIT_read:
; Uses Z-pointer as table index
ldi ZH, 0 ldi ZL, 1
; Preload SPMCSR bits into R16, then write to SPMCSR ldi r16, (1<<RSIG)|(1<<SPMEN)
out SPMCSR, r16
; Issue LPM. Table data will be returned into r17 lpm r17, Z
ret
Note: See “Code Examples” on page 7.
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