ATtiny13
17.2Fuse Bytes
The ATtiny13 has two fuse bytes. Table 17-3 on page 103 and Table 17-4 on page 103 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.
Table 17-3. Fuse High Byte
Fuse Bit |
Bit No |
Description |
Default Value |
– |
7 |
– |
1 (unprogrammed) |
|
|
|
|
– |
6 |
– |
1 (unprogrammed) |
|
|
|
|
– |
5 |
– |
1 (unprogrammed) |
|
|
|
|
SELFPRGEN(1) |
4 |
Self Programming Enable |
1 (unprogrammed) |
DWEN(2) |
3 |
debugWire Enable |
1 (unprogrammed) |
BODLEVEL1(3) |
2 |
Brown-out Detector trigger level |
1 (unprogrammed) |
BODLEVEL0(3) |
1 |
Brown-out Detector trigger level |
1 (unprogrammed) |
RSTDISBL(4) |
0 |
External Reset disable |
1 (unprogrammed) |
Notes: 1. Enables SPM instruction. See “Self-Programming the Flash” on page 97.
2.DWEN must be unprogrammed when lock Bit security is required. See “Program And Data Memory Lock Bits” on page 102.
3.See Table 18-5 on page 119 for BODLEVEL fuse decoding.
4.See “Alternate Functions of Port B” on page 54 for description of RSTDISBL and DWEN fuses. When programming the RSTDISBL fuse, High-voltage Serial programming has to be used to change fuses to perform further programming.
Table 17-4. |
Fuse Low Byte |
|
|
|
|
Fuse Bit |
|
Bit No |
Description |
Default Value |
|
|
|
|
|
|
|
SPIEN(1) |
|
7 |
Enable Serial Programming and Data |
0 |
(programmed) |
|
|
|
Downloading |
(SPI prog. enabled) |
|
EESAVE |
|
6 |
Preserve EEPROM memory through |
1 |
(unprogrammed) |
|
Chip Erase |
(memory not preserved) |
|||
|
|
|
|||
|
|
|
|
|
|
WDTON(2) |
|
5 |
Watchdog Timer always on |
1 |
(unprogrammed) |
CKDIV8(3) |
|
4 |
Divide clock by 8 |
0 |
(programmed) |
SUT1(4) |
|
3 |
Select start-up time |
1 |
(unprogrammed) |
SUT0(4) |
|
2 |
Select start-up time |
0 |
(programmed) |
CKSEL1(5) |
|
1 |
Select Clock source |
1 |
(unprogrammed) |
CKSEL0(5) |
|
0 |
Select Clock source |
0 |
(programmed) |
Notes: 1. The SPIEN fuse is not accessible in SPI Programming mode.
2.Programming this fues will disable the Watchdog Timer Interrupt. See “Watchdog Timer” on page 37 for details.
3.See “System Clock Prescaler” on page 26 for details.
4.The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 18-3 on page 118 for details.
5.The default setting of CKSEL1..0 results in internal RC Oscillator @ 9.6 MHz. See Table 18-3 on page 118 for details.
103
2535J–AVR–08/10