UM1725

HAL RCC Extension Driver

46.3RCCEx Firmware driver defines

46.3.1RCCEx

RCC BitAddress AliasRegion

RCC_PLLSAION_BIT_NUMBER

RCC_CR_PLLSAION_BB

RCC_DCKCFGR_OFFSET

RCC_TIMPRE_BIT_NUMBER

RCC_DCKCFGR_TIMPRE_BB

PLL_TIMEOUT_VALUE

RCC CEC Clock Source

RCC_CECCLKSOURCE_HSI

RCC_CECCLKSOURCE_LSE

RCC CK48 Clock Source

RCC_CK48CLKSOURCE_PLLQ

RCC_CK48CLKSOURCE_PLLSAIP

RCCEx Exported Macros

__HAL_RCC_GPIOF_CLK_ENABLE

__HAL_RCC_GPIOG_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE

__HAL_RCC_USB_OTG_HS_ULPI_CLK_EN ABLE

__HAL_RCC_GPIOF_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE

__HAL_RCC_USB_OTG_HS_ULPI_CLK_DIS ABLE

__HAL_RCC_DCMI_CLK_ENABLE

__HAL_RCC_DCMI_CLK_DISABLE __HAL_RCC_FMC_CLK_ENABLE

Notes:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Notes:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Notes:

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HAL RCC Extension Driver

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__HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_FMC_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_TIM6_CLK_ENABLE

__HAL_RCC_TIM7_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE __HAL_RCC_SPDIFRX_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE __HAL_RCC_FMPI2C1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE __HAL_RCC_TIM6_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE __HAL_RCC_SPDIFRX_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE __HAL_RCC_FMPI2C1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Notes:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

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DOCID025834 Rev 2

UM1725

HAL RCC Extension Driver

__HAL_RCC_CEC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE __HAL_RCC_TIM8_CLK_ENABLE

__HAL_RCC_ADC2_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE __HAL_RCC_TIM8_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE __HAL_RCC_GPIOF_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET

__HAL_RCC_USB_OTG_HS_FORCE_RESE T

__HAL_RCC_GPIOF_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET

__HAL_RCC_USB_OTG_HS_RELEASE_RE SET

__HAL_RCC_DCMI_FORCE_RESET __HAL_RCC_DCMI_RELEASE_RESET __HAL_RCC_FMC_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_FMC_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_TIM6_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET __HAL_RCC_SPDIFRX_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET

Notes:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

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__HAL_RCC_UART4_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET __HAL_RCC_FMPI2C1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET __HAL_RCC_TIM6_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET __HAL_RCC_SPDIFRX_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET __HAL_RCC_FMPI2C1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET __HAL_RCC_TIM8_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET __HAL_RCC_TIM8_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE

__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE

__HAL_RCC_USB_OTG_HS_CLK_SLEEP_E NABLE

Notes:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. After wakeup from SLEEP mode, the peripheral clock is enabled again. By default, all peripheral clocks are enabled during SLEEP mode.

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DOCID025834 Rev 2

UM1725

HAL RCC Extension Driver

__HAL_RCC_USB_OTG_HS_ULPI_CLK_SL EEP_ENABLE

__HAL_RCC_GPIOF_CLK_SLEEP_DISABLE

__HAL_RCC_GPIOG_CLK_SLEEP_DISABL E

__HAL_RCC_SRAM2_CLK_SLEEP_DISABL E

__HAL_RCC_USB_OTG_HS_CLK_SLEEP_ DISABLE

__HAL_RCC_USB_OTG_HS_ULPI_CLK_SL EEP_DISABLE

__HAL_RCC_DCMI_CLK_SLEEP_ENABLE

__HAL_RCC_DCMI_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE

__HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE

__HAL_RCC_TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE __HAL_RCC_SPDIFRX_CLK_SLEEP_ENAB

Notes:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. After wakeup from SLEEP mode, the peripheral clock is enabled again. By default, all peripheral clocks are enabled during SLEEP mode.

Notes:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. After wakeup from SLEEP mode, the peripheral clock is enabled again. By default, all peripheral clocks are enabled during SLEEP mode.

Notes:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. After wakeup from SLEEP mode, the peripheral clock is enabled again. By default, all peripheral clocks are enabled during SLEEP mode.

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HAL RCC Extension Driver	UM1725
LE
__HAL_RCC_USART3_CLK_SLEEP_ENABL
E
__HAL_RCC_UART4_CLK_SLEEP_ENABLE
__HAL_RCC_UART5_CLK_SLEEP_ENABLE
__HAL_RCC_FMPI2C1_CLK_SLEEP_ENAB
LE
__HAL_RCC_CAN1_CLK_SLEEP_ENABLE
__HAL_RCC_CAN2_CLK_SLEEP_ENABLE
__HAL_RCC_CEC_CLK_SLEEP_ENABLE
__HAL_RCC_DAC_CLK_SLEEP_ENABLE
__HAL_RCC_TIM6_CLK_SLEEP_DISABLE
__HAL_RCC_TIM7_CLK_SLEEP_DISABLE
__HAL_RCC_TIM12_CLK_SLEEP_DISABLE
__HAL_RCC_TIM13_CLK_SLEEP_DISABLE
__HAL_RCC_TIM14_CLK_SLEEP_DISABLE
__HAL_RCC_SPDIFRX_CLK_SLEEP_DISAB
LE
__HAL_RCC_USART3_CLK_SLEEP_DISAB
LE
__HAL_RCC_UART4_CLK_SLEEP_DISABL
E
__HAL_RCC_UART5_CLK_SLEEP_DISABL
E
__HAL_RCC_FMPI2C1_CLK_SLEEP_DISAB
LE
__HAL_RCC_CAN1_CLK_SLEEP_DISABLE
__HAL_RCC_CAN2_CLK_SLEEP_DISABLE
__HAL_RCC_CEC_CLK_SLEEP_DISABLE
__HAL_RCC_DAC_CLK_SLEEP_DISABLE
__HAL_RCC_TIM8_CLK_SLEEP_ENABLE	Notes:

__HAL_RCC_ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. After wakeup from SLEEP mode, the peripheral clock is enabled again. By default, all peripheral clocks are enabled during SLEEP mode.

590/900

DOCID025834 Rev 2

UM1725

HAL RCC Extension Driver

__HAL_RCC_SAI2_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE __HAL_RCC_PLL_CONFIG

Description:

Macro to configure the main PLL clock source, multiplication and division factors.

Parameters:

__RCC_PLLSource__: specifies the PLL entry clock source. This parameter can be one of the following values:

RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry

RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

__PLLM__: specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

__PLLN__: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 192 and Max_Data = 432.

__PLLP__: specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.

__PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.

__PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Notes:

This function must be used only when the main PLL is disabled.

This clock source (RCC_PLLSource)

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HAL RCC Extension Driver			UM1725
			is common for the main PLL and
			PLLI2S.
			You have to set the PLLM parameter
			correctly to ensure that the VCO
			input frequency ranges from 1 to 2
			MHz. It is recommended to select a
			frequency of 2 MHz to limit PLL jitter.
			You have to set the PLLN parameter
			correctly to ensure that the VCO
			output frequency is between 192 and
			432 MHz.
			If the USB OTG FS is used in your
			application, you have to set the
			PLLQ parameter correctly to have 48
			MHz clock for the USB. However, the
			SDIO and RNG need a frequency
			lower than or equal to 48 MHz to
			work correctly.
			This parameter is only available in
			STM32F446xx devices.
	__HAL_RCC_PLLI2S_CONFIG	Description:
			Macro to configure the PLLI2S clock
			multiplication and division factors .
		Parameters:
			__PLLI2SM__: specifies the division
			factor for PLLI2S VCO input clock
			This parameter must be a number
			between Min_Data = 2 and
			Max_Data = 63.
			__PLLI2SN__: specifies the
			multiplication factor for PLLI2S VCO
			output clock This parameter must be
			a number between Min_Data = 192
			and Max_Data = 432.
			__PLLI2SP__: specifies division
			factor for SPDIFRX Clock. This
			parameter must be a number in the
			range {2, 4, 6, or 8}.
			__PLLI2SR__: specifies the division
			factor for I2S clock This parameter
			must be a number between
			Min_Data = 2 and Max_Data = 7.
			__PLLI2SQ__: specifies the division
			factor for SAI clock This parameter
			must be a number between
			Min_Data = 2 and Max_Data = 15.
		Notes:
			This macro must be used only when
			the PLLI2S is disabled. PLLI2S clock
			source is common with the main PLL
			(configured in
			HAL_RCC_ClockConfig() API).
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UM1725	HAL RCC Extension Driver
	You have to set the PLLI2SM
	parameter correctly to ensure that
	the VCO input frequency ranges from
	1 to 2 MHz. It is recommended to
	select a frequency of 1 MHz to limit
	PLLI2S jitter. The PLLI2SM
	parameter is only used with
	STM32F411xE and STM32F446xx
	Devices
	You have to set the PLLI2SN
	parameter correctly to ensure that
	the VCO output frequency is
	between Min_Data = 192 and
	Max_Data = 432 MHz.
	the PLLI2SP parameter is only
	available with STM32F446xx
	Devices
	You have to set the PLLI2SR
	parameter correctly to not exceed
	192 MHz on the I2S clock frequency.
	the PLLI2SQ parameter is only
	available with
	STM32F427/437/429x/439xx
	Devices

__HAL_RCC_PLLSAI_ENABLE	Notes:
		The PLLSAI is only available with
		STM32F429x/439x Devices. The
		PLLSAI is disabled by hardware
		when entering STOP and STANDBY
		modes.
__HAL_RCC_PLLSAI_DISABLE
__HAL_RCC_PLLSAI_CONFIG	Description:
		Macro to configure the PLLSAI clock
		multiplication and division factors.
	Parameters:
		__PLLSAIM__: specifies the division
		factor for PLLSAI VCO input clock
		This parameter must be a number
		between Min_Data = 2 and
		Max_Data = 63.
		__PLLSAIN__: specifies the
		multiplication factor for PLLSAI VCO
		output clock. This parameter must be
		a number between Min_Data = 192
		and Max_Data = 432.
		__PLLSAIP__: specifies division
		factor for OTG FS, SDIO and RNG
		clocks. This parameter must be a
		number in the range {2, 4, 6, or 8}.
		__PLLSAIQ__: specifies the division
		factor for SAI clock This parameter
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__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CO NFIG

must be a number between Min_Data = 2 and Max_Data = 15.

__PLLSAIR__: specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Notes:

You have to set the PLLSAIM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 1 MHz to limit PLLI2S jitter. The PLLSAIM parameter is only used with STM32F446xx Devices

You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 192 and Max_Data = 432 MHz.

the PLLSAIP parameter is only available with STM32F446xx Devices

the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices

Description:

Macro to configure the SAI clock Divider coming from PLLI2S.

Parameters:

__PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock

. This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__

Notes:

This function must be called before enabling the PLLI2S.

__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CO NFIG

Description:

Macro to configure the SAI clock Divider coming from PLLSAI.

Parameters:

__PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock

. This parameter must be a number between Min_Data = 1 and Max_Data = 32. SAI1 clock frequency = f(PLLSAIQ) /

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		__PLLSAIDivQ__
	Notes:
		This function must be called before
		enabling the PLLSAI.
__HAL_RCC_SAI1_CONFIG	Description:
		Macro to configure SAI1 clock source
		selection.
	Parameters:
		__SOURCE__: specifies the SAI1
		clock source. This parameter can be
		one of the following values:
			RCC_SAI1CLKSOURCE_PLLI2
			S: PLLI2S_Q clock divided by
			PLLI2SDIVQ used as SAI1
			clock.
			RCC_SAI1CLKSOURCE_PLLS
			AI: PLLISAI_Q clock divided by
			PLLSAIDIVQ used as SAI1
			clock.
			RCC_SAI1CLKSOURCE_PLLR:
			PLL VCO Output divided by
			PLLR used as SAI1 clock.
			RCC_SAI1CLKSOURCE_EXT:
			External clock mapped on the
			I2S_CKIN pin used as SAI1
			clock.
	Notes:
		This configuration is only available
		with STM32F446xx Devices. This
		function must be called before
		enabling PLL, PLLSAI, PLLI2S and
		the SAI clock.
__HAL_RCC_GET_SAI1_SOURCE	Description:
		Macro to Get SAI1 clock source
		selection.
	Return value:
		The: clock source can be one of the
		following values:
			RCC_SAI1CLKSOURCE_PLLI2
			S: PLLI2S_Q clock divided by
			PLLI2SDIVQ used as SAI1
			clock.
			RCC_SAI1CLKSOURCE_PLLS
			AI: PLLISAI_Q clock divided by
			PLLSAIDIVQ used as SAI1
			clock.
			RCC_SAI1CLKSOURCE_PLLR:
			PLL VCO Output divided by
			PLLR used as SAI1 clock.
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HAL RCC Extension Driver	UM1725
	RCC_SAI1CLKSOURCE_EXT:
	External clock mapped on the
	I2S_CKIN pin used as SAI1
	clock.

		Notes:
			This configuration is only available
			with STM32F446xx Devices.
	__HAL_RCC_SAI2_CONFIG	Description:
			Macro to configure SAI2 clock source
			selection.
		Parameters:
			__SOURCE__: specifies the SAI2
			clock source. This parameter can be
			one of the following values:
				RCC_SAI2CLKSOURCE_PLLI2
				S: PLLI2S_Q clock divided by
				PLLI2SDIVQ used as SAI2
				clock.
				RCC_SAI2CLKSOURCE_PLLS
				AI: PLLISAI_Q clock divided by
				PLLSAIDIVQ used as SAI2
				clock.
				RCC_SAI2CLKSOURCE_PLLR:
				PLL VCO Output divided by
				PLLR used as SAI2 clock.
				RCC_SAI2CLKSOURCE_PLLS
				RC: HSI or HSE depending from
				PLL Source clock used as SAI2
				clock.
		Notes:
			This configuration is only available
			with STM32F446xx Devices. This
			function must be called before
			enabling PLL, PLLSAI, PLLI2S and
			the SAI clock.
	__HAL_RCC_GET_SAI2_SOURCE	Description:
			Macro to Get SAI2 clock source
			selection.
		Return value:
			The: clock source can be one of the
			following values:
				RCC_SAI2CLKSOURCE_PLLI2
				S: PLLI2S_Q clock divided by
				PLLI2SDIVQ used as SAI2
				clock.
				RCC_SAI2CLKSOURCE_PLLS
				AI: PLLISAI_Q clock divided by
				PLLSAIDIVQ used as SAI2
				clock.
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	RCC_SAI2CLKSOURCE_PLLR:
	PLL VCO Output divided by
	PLLR used as SAI2 clock.
	RCC_SAI2CLKSOURCE_PLLS
	RC: HSI or HSE depending from
	PLL Source clock used as SAI2
	clock.

	Notes:
		This configuration is only available
		with STM32F446xx Devices.
__HAL_RCC_I2S_APB1_CONFIG	Description:
		Macro to configure I2S APB1 clock
		source selection.
	Parameters:
		__SOURCE__: specifies the I2S
		APB1 clock source. This parameter
		can be one of the following values:
		RCC_I2SAPB1CLKSOURCE_P
		LLI2S: PLLI2S VCO output
		clock divided by PLLI2SR used
		as I2S clock.
		RCC_I2SAPB1CLKSOURCE_E
		XT: External clock mapped on
		the I2S_CKIN pin used as SAI1
		clock.
		RCC_I2SAPB1CLKSOURCE_P
		LLR: PLL VCO Output divided
		by PLLR used as SAI1 clock.
		RCC_I2SAPB1CLKSOURCE_P
		LLSRC: HSI or HSE depending
		from PLL source Clock.
	Notes:
		This configuration is only available
		with STM32F446xx Devices. This
		function must be called before
		enabling PLL, PLLI2S and the I2S
		clock.
__HAL_RCC_GET_I2S_APB1_SOURCE	Description:
		Macro to Get I2S APB1 clock source
		selection.
	Return value:
		The: clock source can be one of the
		following values:
		RCC_I2SAPB1CLKSOURCE_P
		LLI2S: PLLI2S VCO output
		clock divided by PLLI2SR used
		as I2S clock.
		RCC_I2SAPB1CLKSOURCE_E
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HAL RCC Extension Driver	UM1725
	XT: External clock mapped on
	the I2S_CKIN pin used as SAI1
	clock.
	RCC_I2SAPB1CLKSOURCE_P
	LLR: PLL VCO Output divided
	by PLLR used as SAI1 clock.
	RCC_I2SAPB1CLKSOURCE_P
	LLSRC: HSI or HSE depending
	from PLL source Clock.

		Notes:
			This configuration is only available
			with STM32F446xx Devices.
	__HAL_RCC_I2S_APB2_CONFIG	Description:
			Macro to configure I2S APB2 clock
			source selection.
		Parameters:
			__SOURCE__: specifies the SAI
			Block A clock source. This parameter
			can be one of the following values:
			RCC_I2SAPB2CLKSOURCE_P
			LLI2S: PLLI2S VCO output
			clock divided by PLLI2SR used
			as I2S clock.
			RCC_I2SAPB2CLKSOURCE_E
			XT: External clock mapped on
			the I2S_CKIN pin used as SAI1
			clock.
			RCC_I2SAPB2CLKSOURCE_P
			LLR: PLL VCO Output divided
			by PLLR used as SAI1 clock.
			RCC_I2SAPB2CLKSOURCE_P
			LLSRC: HSI or HSE depending
			from PLL source Clock.
		Notes:
			This configuration is only available
			with STM32F446xx Devices. This
			function must be called before
			enabling PLL, PLLI2S and the I2S
			clock.
	__HAL_RCC_GET_I2S_APB2_SOURCE	Description:
			Macro to Get I2S APB2 clock source
			selection.
		Return value:
			The: clock source can be one of the
			following values:
			RCC_I2SAPB2CLKSOURCE_P
			LLI2S: PLLI2S VCO output
			clock divided by PLLI2SR used
			as I2S clock.
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UM1725	HAL RCC Extension Driver
	RCC_I2SAPB2CLKSOURCE_E
	XT: External clock mapped on
	the I2S_CKIN pin used as SAI1
	clock.
	RCC_I2SAPB2CLKSOURCE_P
	LLR: PLL VCO Output divided
	by PLLR used as SAI1 clock.
	RCC_I2SAPB2CLKSOURCE_P
	LLSRC: HSI or HSE depending
	from PLL source Clock.

	Notes:
		This configuration is only available
		with STM32F446xx Devices.
__HAL_RCC_CEC_CONFIG	Description:
		Macro to configure the CEC clock.
	Parameters:
		__SOURCE__: specifies the CEC
		clock source. This parameter can be
		one of the following values:
		RCC_CECCLKSOURCE_HSI:
		HSI selected as CEC clock
		RCC_CECCLKSOURCE_LSE:
		LSE selected as CEC clock
__HAL_RCC_GET_CEC_SOURCE	Description:
		Macro to Get the CEC clock.
	Return value:
		The: clock source can be one of the
		following values:
		RCC_CECCLKSOURCE_HSI48
		8: HSI selected as CEC clock
		RCC_CECCLKSOURCE_LSE:
		LSE selected as CEC clock
__HAL_RCC_FMPI2C1_CONFIG	Description:
		Macro to configure the FMPI2C1
		clock.
	Parameters:
		__SOURCE__: specifies the
		FMPI2C1 clock source. This
		parameter can be one of the
		following values:
		RCC_FMPI2C1CLKSOURCE_A
		PB: APB selected as CEC clock
		RCC_FMPI2C1CLKSOURCE_S
		YSCLK: SYS clock selected as
		CEC clock
		RCC_FMPI2C1CLKSOURCE_H
		SI: HSI selected as CEC clock
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HAL RCC Extension Driver				UM1725
	__HAL_RCC_GET_FMPI2C1_SOURCE	Description:
			Macro to Get the FMPI2C1 clock.
		Return value:
			The: clock source can be one of the
			following values:
			RCC_FMPI2C1CLKSOURCE_A
				PB: APB selected as CEC clock
			RCC_FMPI2C1CLKSOURCE_S
				YSCLK: SYS clock selected as
				CEC clock
			RCC_FMPI2C1CLKSOURCE_H
				SI: HSI selected as CEC clock
	__HAL_RCC_CLK48_CONFIG	Description:
			Macro to configure the CLK48 clock.
		Parameters:
			__SOURCE__: specifies the CK48
			clock source. This parameter can be
			one of the following values:
			RCC_CK48CLKSOURCE_PLL
				Q: PLL VCO Output divided by
				PLLQ used as CK48 clock.
			RCC_CK48CLKSOURCE_PLL
				SAIP: PLLSAI VCO Output
				divided by PLLSAIP used as
				CK48 clock.
	__HAL_RCC_GET_CLK48_SOURCE	Description:
			Macro to Get the CLK48 clock.
		Return value:
			The: clock source can be one of the
			following values:
			RCC_CK48CLKSOURCE_PLL
				Q: PLL VCO Output divided by
				PLLQ used as CK48 clock.
			RCC_CK48CLKSOURCE_PLL
				SAIP: PLLSAI VCO Output
				divided by PLLSAIP used as
				CK48 clock.
	__HAL_RCC_SDIO_CONFIG	Description:
			Macro to configure the SDIO clock.
		Parameters:
			__SOURCE__: specifies the SDIO
			clock source. This parameter can be
			one of the following values:
				RCC_SDIOCLKSOURCE_CK48
				: CK48 output used as SDIO
				clock.
				RCC_SDIOCLKSOURCE_SYS
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UM1725		HAL RCC Extension Driver
		CLK: System clock output used
		as SDIO clock.
__HAL_RCC_GET_SDIO_SOURCE	Description:
		Macro to Get the SDIO clock.
	Return value:
		The: clock source can be one of the
		following values:
		RCC_SDIOCLKSOURCE_CK48
		: CK48 output used as SDIO
		clock.
		RCC_SDIOCLKSOURCE_SYS
		CLK: System clock output used
		as SDIO clock.
__HAL_RCC_SPDIFRX_CONFIG	Description:
		Macro to configure the SPDIFRX
		clock.
	Parameters:
		__SOURCE__: specifies the
		SPDIFRX clock source. This
		parameter can be one of the
		following values:
		RCC_SPDIFRXCLKSOURCE_
		PLLR: PLL VCO Output divided
		by PLLR used as SPDIFRX
		clock.
		RCC_SPDIFRXCLKSOURCE_
		PLLI2SP: PLLI2S VCO Output
		divided by PLLI2SP used as
		SPDIFRX clock.
__HAL_RCC_GET_SPDIFRX_SOURCE	Description:
		Macro to Get the SPDIFRX clock.
	Return value:
		The: clock source can be one of the
		following values:
		RCC_SPDIFRXCLKSOURCE_
		PLLR: PLL VCO Output divided
		by PLLR used as SPDIFRX
		clock.
		RCC_SPDIFRXCLKSOURCE_
		PLLI2SP: PLLI2S VCO Output
		divided by PLLI2SP used as
		SPDIFRX clock.
__HAL_RCC_TIMCLKPRESCALER	Description:
		Macro to configure the Timers clocks
		prescalers.
	Parameters:
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HAL RCC Extension Driver

UM1725

__HAL_RCC_PLLSAI_ENABLE_IT __HAL_RCC_PLLSAI_DISABLE_IT __HAL_RCC_PLLSAI_CLEAR_IT __HAL_RCC_PLLSAI_GET_IT

__HAL_RCC_PLLSAI_GET_FLAG

RCC FMPI2C1 Clock Source

RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_SYSCLK RCC_FMPI2C1CLKSOURCE_HSI

RCC I2S APB1 Clock Source

RCC_I2SAPB1CLKSOURCE_PLLI2S RCC_I2SAPB1CLKSOURCE_EXT RCC_I2SAPB1CLKSOURCE_PLLR

__PRESC__: : specifies the Timers clocks prescalers selection This parameter can be one of the following values:

RCC_TIMPRES_DESACTIVAT ED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.

RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.

Notes:

This feature is only available with STM32F429x/439x Devices.

Description:

Check the PLLSAI RDY interrupt has occurred or not.

Return value:

The: new state (TRUE or FALSE).

Description:

Check PLLSAI RDY flag is set or not.

Return value:

The: new state (TRUE or FALSE).

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DOCID025834 Rev 2

UM1725	HAL RCC Extension Driver
RCC_I2SAPB1CLKSOURCE_PLLSRC
RCC I2S APB2 Clock Source
RCC_I2SAPB2CLKSOURCE_PLLI2S
RCC_I2SAPB2CLKSOURCE_EXT
RCC_I2SAPB2CLKSOURCE_PLLR
RCC_I2SAPB2CLKSOURCE_PLLSRC
RCC Private macros to check input parameters
IS_RCC_PERIPHCLOCK
IS_RCC_PLLI2SN_VALUE
IS_RCC_PLLI2SR_VALUE
IS_RCC_PLLI2SQ_VALUE
IS_RCC_PLLSAIN_VALUE
IS_RCC_PLLSAIQ_VALUE
IS_RCC_PLLSAIR_VALUE
IS_RCC_PLLSAI_DIVQ_VALUE
IS_RCC_PLLI2S_DIVQ_VALUE
IS_RCC_PLLSAI_DIVR_VALUE
IS_RCC_PLLI2SM_VALUE
IS_RCC_LSE_MODE
IS_RCC_PLLR_VALUE
IS_RCC_PLLI2SP_VALUE
IS_RCC_PLLSAIM_VALUE
IS_RCC_PLLSAIP_VALUE
IS_RCC_SAI1CLKSOURCE
IS_RCC_SAI2CLKSOURCE
IS_RCC_I2SAPB1CLKSOURCE
IS_RCC_I2SAPB2CLKSOURCE
IS_RCC_FMPI2C1CLKSOURCE
IS_RCC_CECCLKSOURCE
IS_RCC_CK48CLKSOURCE
IS_RCC_SDIOCLKSOURCE
IS_RCC_SPDIFRXCLKSOURCE
RCC LSE Dual Mode Selection
RCC_LSE_LOWPOWER_MODE
RCC_LSE_HIGHDRIVE_MODE
RCC Periph Clock Selection
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HAL RCC Extension Driver

UM1725

RCC_PERIPHCLK_I2S_APB1

RCC_PERIPHCLK_I2S_APB2

RCC_PERIPHCLK_SAI1

RCC_PERIPHCLK_SAI2

RCC_PERIPHCLK_TIM

RCC_PERIPHCLK_RTC

RCC_PERIPHCLK_CEC

RCC_PERIPHCLK_FMPI2C1

RCC_PERIPHCLK_CK48

RCC_PERIPHCLK_SDIO

RCC_PERIPHCLK_SPDIFRX

RCC_PERIPHCLK_PLLI2S

RCC PLLI2SP Clock Divider

RCC_PLLI2SP_DIV2

RCC_PLLI2SP_DIV4

RCC_PLLI2SP_DIV6

RCC_PLLI2SP_DIV8

RCC PLLSAIP Clock Divider

RCC_PLLSAIP_DIV2

RCC_PLLSAIP_DIV4

RCC_PLLSAIP_DIV6

RCC_PLLSAIP_DIV8

RCC PLLSAI DIVR

RCC_PLLSAIDIVR_2

RCC_PLLSAIDIVR_4

RCC_PLLSAIDIVR_8

RCC_PLLSAIDIVR_16

RCC SAI1 Clock Source

RCC_SAI1CLKSOURCE_PLLSAI

RCC_SAI1CLKSOURCE_PLLI2S

RCC_SAI1CLKSOURCE_PLLR

RCC_SAI1CLKSOURCE_EXT

RCC SAI2 Clock Source

RCC_SAI2CLKSOURCE_PLLSAI

RCC_SAI2CLKSOURCE_PLLI2S

RCC_SAI2CLKSOURCE_PLLR

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DOCID025834 Rev 2

UM1725 HAL RCC Extension Driver

RCC_SAI2CLKSOURCE_PLLSRC

RCC SDIO Clock Source

RCC_SDIOCLKSOURCE_CK48

RCC_SDIOCLKSOURCE_SYSCLK

RCC SPDIFRX Clock Source

RCC_SPDIFRXCLKSOURCE_PLLR

RCC_SPDIFRXCLKSOURCE_PLLI2SP

RCC TIM PRescaler Selection

RCC_TIMPRES_DESACTIVATED

RCC_TIMPRES_ACTIVATED

DOCID025834 Rev 2

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