EIGRP checks its topology table for a suitable new route to the destination. If a route exists in the table, EIGRP updates the routing table with the new route and purges the old route from the table. Unlike other routing protocols, EIGRP saves WAN−link bandwidth by sending routing updates only when routing information changes. It also takes into account the available bandwidth between the paths to determine the rate at which it transmits updates.

∙Open Shortest Path First—OSPF is an IP−based link−state routing protocol designed to overcome the limitations of RIP. It sends link−state advertisements (LSAs) to all other routers within the network. Information is included in the LSAs about the interfaces on which OSPF is running and the metrics used. As routers collect the link−state information, they use the Shortest Path First (SPF) algorithm to calculate the shortest path to each node.

∙Routing Information Protocol—RIP is another distance−vector routing protocol that works well in small networks. However, in larger, more complex internetworks, RIP has many limitations, such as a maximum hop count of 15, lack of support for variable−length subnet masks (VLSMs), slow convergence, and inefficient use of bandwidth.

Routing Protocol Assignment

All devices communicate with each other through a path or route. If the destination interface does not reside in the same network segments as the sender, a route to the destination must be found using a dynamic routing protocol or a static route. If you have stacks of cash to spend on IOSs for your internal route processors, you can support any number of the following routing protocols:

∙Enhanced Interior Gateway Routing Protocol (EIGRP)

∙Hot Standby Routing Protocol (HSRP)

∙Interior Gateway Routing Protocol (IGRP)

∙NetWare Link Services Protocol (NLSP)

∙Open Shortest Path First (OSPF)

∙Routing Information Protocol (RIP)

∙Routing Table Maintenance Protocol (RTMP) for AppleTalk

To use a dynamic protocol, you must first assign a routing protocol to the route processor being configured just as you would an external router. Then, you identify the network and, in some cases, an area ID and an autonomous system number.

Supervisor Engine Modules

The Supervisor Engine (SE) is basically the brains of the Cisco 4000, 5000, and 6000 families of switches. There are three series of Supervisor Engines; each has its own individual features and the newer ones add features that go beyond those of their predecessors. Let’s take a look at the features of each Supervisor Engine.

Supervisor Engines I and II

As shown in Figure 6.1, the SE I and SE II provide a switching engine using a 25MHz Motorola MC68EC040 Network Management Processor (NMP). The processor’s ability to switch more than one million packets per second (pps) provides data path and data control for all the switch’s network interfaces, including two on−board integrated Fast Ethernet interfaces that can support redundancy using the Spanning−Tree Algorithm or load sharing. Other features supported by these SEs are:

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Figure 6.1: The Catalyst Supervisor Engine I and II.

∙Media Access Control Addressing and VLANs—Support for 16,000 active MAC addresses for up to 1,024 VLANs allocated dynamically between active ports.

∙Management—Support for Simple Network Management Protocol (SNMP) for statistical management. The SE also supports access and management through the console and Telnet interface.

The SE II includes a few upgraded features, such as:

∙Support for redundant supervisor engines

∙Support for redundant clock modules

∙Support for core−switching logic

The Supervisor Engine II G supports additional features, such as:

∙An optional NetFlow Feature Card II (NFFC II) chipset built in

∙Route Switch Feature Card (RSFC)

∙Modular uplink ports

Supervisor Engine III

The Supervisor Engine III is available in three models:

∙Supervisor Engine III with Enhanced Address Recognition Logic (EARL) ASIC

∙Supervisor Engine III with the NFFC

∙Supervisor Engine III with the NFFC II

The Supervisor Engine III shown in Figure 6.2 has a few more features than SEs I and II:

Figure 6.2: The Supervisor Engine III.

∙150MHz RISC 4700 processor

∙Three switching buses that can simultaneously provide 1.2GB of throughput, resulting in a 3.6Gbps throughput engine

∙Two Flash PC card slots that can be used for memory upgrades or to serve as additional I/O devices

The Supervisor Engine III G shown in Figure 6.3 provides the following additional features:

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