Fundamentals of Microelectronics

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	341 (1)

Sec. 7.3 Common-Gate Stage

341

as

VGS = 0:947 V:	(7.97)
For M1 to remain in saturation,
VDD , IDRD > Vb , VTH	(7.98)
and hence
RD < 2:71 k :	(7.99)
Also, the above value of W=L and ID yield gm = (447 ),1 and
Av 6:06:	(7.100)

Figure 7.22 summarizes the allowable signal levels in this design. The gate voltage can be generated using a resistive divider similar to that in Fig. 7.20(a).

Vb − VTH = 0.447 V

0

Figure 7.22 Signal levels in CG stage.

VDD

RD

Vout Vb = 0.947 V

M 1

Vin

Exercise

If a gain of 10 is required, what value should be chosen for W=L?

We now compute the I/O impedances of the CG stage, expecting to obtain results similar to those of the CB topology. Neglecting channel-length modulation for now, we have from Fig. 7.23(a) v1 = ,vX and

			i X
v 1	gmv 1 RD	v 1	gmv 1 RD	v X

i X

v X

(a)

(b)

Figure 7.23 (a) Input and (b) output impedances of CG stage.

iX = ,gmv1	(7.101)
= gmvX :	(7.102)

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342			Chap. 7 CMOS Amplifiers
That is,
Rin =	1	;	(7.103)
	gm
a relatively low value. Also, from Fig. 7.23(b), v1 = 0 and hence
Rout = RD;			(7.104)

an expected result because the circuits of Figs. 7.23(b) and 7.7 are identical.

Let us study the behavior of the CG stage in the presence of a finite source impedance (Fig. 7.24) but still with = 0. In a manner similar to that depicted in Chapter 5 for the CB topology,

we write

VDD

		RD
		Vout
	RS M 1	Vb		RS v X
		X		1
v in			v in
	1			g m
	g m

Figure 7.24 Simplification of CG stage with signal source resistance.

			1
vX =			gm		vin
	1		+ RS
		gm
=			1			vin:
	1 + gmRS

Thus,

vout = vout					vX
vin		vX		vin
=		gmRD
	1 + gmRS
=		RD				:
	1
				+ RS
		gm

(7.105)

(7.106)

(7.107)

(7.108)

(7.109)

The gain is therefore equal to that of the degenerated CS stage except for a negative sign.

In contrast to the common-source stage, the CG amplifier exhibits a current gain of unity: the current provided by the input voltage source simply flows through the channel and emerges from the drain node.

The analysis of the common-gate stage in the general case, i.e., including both channel-length modulation and a finite source impedance is beyond the scope of this book (Problem 41). However, we can make two observations. First, a resistance appearing in series with the gate terminal [Fig. 7.25(a)] does not alter the gain or I/O impedances (at low frequencies) because it sustains

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	343 (1)

Sec. 7.3 Common-Gate Stage		343
VDD
RD		R out
Vout
M 1	Vb	r O
		RS
R G		M 1
v in
(a)		(b)

Figure 7.25 (a) CG stage with gate resistance, (b) output resistance of CG stage.

a zero potential drop—as if its value were zero. Second, the output resistance of the CG stage in the general case [Fig. 7.25(b)] is identical to that of the degenerated CS topology:

Rout = (1 + gmrO)RS + rO:

(7.110)

Example 7.13

For the circuit shown in Fig. 7.26(a), calculate the voltage gain if = 0 and the output impedance if > 0.

		VDD					R out1
		RD
		Vout		1		r O1
				g	m1
RS	M 1	Vb		RS		RS
					v X	M 1
	X
Vin			v in	1		1
	M 2						r O2
				g m2		g m2
	(a)			(b)		(c)

Figure 7.26 (a) Example of CG stage, (b) equivalent input network, (c) calculation of output resistance.

Solution

We first compute vX=vin with the aid of the equivalent circuit depicted in Fig. 7.26(b):

	1					jj	1
vX =
			gm2				gm1					(7.111)
	1					1
vin								+ RS
		gm2 jjgm1
=							1				:	(7.112)
	1 + (gm1 + gm2)RS

Noting that vout=vX = gm1RD, we have

vout =	gm1RD	:	(7.113)
vin	1 + (gm1 + gm2)RS

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	344 (1)

344 Chap. 7 CMOS Amplifiers

To compute the output impedance, we first consider

Rout1, as shown in Fig. 7.26(c), which

from (7.110) is equal to

R

= (1 + g

r

)(

1

jjr

jjR ) + r

(7.114)

O2

O1

out1

m1

O1

gm2

S

g

r

(

1

jjR

) + r

:

(7.115)

m1

O1

gm2

S

O1

The overall output impedance is then given by

Rout = Rout1jjRD

(7.116)

[g

r

(

1

jjR

) + r

]jjR

:

(7.117)

m1

O1

gm2

S

O1

D

Exercise

Calculate the output impedance if the gate of M2 is tied to a constant voltage.

7.3.1 CG Stage With Biasing

Following our study of the CB biasing in Chapter 5, we surmise the CG amplifier can be biased as shown in Fig. 7.27. Providing a path for the bias current to ground, resistor R3 lowers the input impedance—and hence the voltage gain—if the signal source exhibits a finite output impedance,

RS.

VDD

	RD	R1
		Vout
RS	M 1
	X	R2
Vin

C1

R3

Figure 7.27 CG stage with biasing.

Since the impedance seen to the right of node X is equal to R3jj(1=gm), we have

vout = vX		vout		(7.118)
vin	vin	vX
=		R3jj(1=gm)	gmRD;	(7.119)
	R3jj(1=gm) + RS

where channel-length modulation is neglected. As mentioned earlier, the voltage divider consisting of R1 and R2 does not affect the small-signal behavior of the circuit (at low frequencies).

Example 7.14

Design the common-gate stage of Fig. 7.27 for the following parameters: vout=vin = 5,

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	345 (1)

Sec. 7.3 Common-Gate Stage

345

RS = 0, R3 = 500 , 1=gm = 50 , power budget = 2 mW, VDD = 1:8 V. AssumenCox = 100 A=V2, VTH = 0:5 V, and = 0.

Solution

From the power budget, we obtain a total supply current of 1.11 mA. Allocating 10 A to the voltage divider, R1 and R2, we leave 1.1 mA for the drain current of M1. Thus, the voltage drop across R3 is equal to 550 mV.

We must now compute two interrelated parameters: W=L and RD. A larger value of W=L yields a greater gm, allowing a lower value of RD. As in Example 7.11, we choose an initial value for VGS to arrive at a reasonable guess for W=L. For example, if VGS = 0:8 V, then

W=L = 244, and gm = 2ID=(VGS , VTH) = (136:4 ),1, dictating RD = 682 for

vout=vin = 5.

Let us determine whether M1 operates in saturation. The gate voltage is equal to VGS plus the drop across R3, amounting to 1.35 V. On the other hand, the drain voltage is given by VDD , IDRD = 1:05 V. Since the drain voltage exceeds VG , VTH , M1 is indeed in saturation.

The resistive divider consisting of R1 and R2 must establish a gate voltage equal to 1.35 V while drawing 10 A:

	VDD		= 10 A	(7.120)
	R1 + R2
R2				(7.121)
		VDD = 1:35 V:
R1 + R2

It follows that R1 = 45 k and R2 = 135 k .

Exercise

If W=L cannot exceed 100, what voltage gain can be achieved?

Example 7.15

Suppose in Example 7.14, we wish to minimize W=L (and hence transistor capacitances). What is the minimum acceptable value of W=L?

Solution

For a given ID, as W=L decreases, VGS , VTH increases. Thus, we must first compute the maximum allowable VGS. We impose the condition for saturation as

VDD , IDRD > VGS + VR3 , VTH ;

(7.122)

where VR3 denotes the voltage drop across R3, and set gmRD to the required gain:

			2ID	RD = Av:				(7.123)
			VGS , VTH
Eliminating RD from (7.122) and (7.123) gives:
V	DD	, Av (V , V		) > V , V	TH	+ V	R3	(7.124)
		2	GS TH	GS

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	346 (1)

346										Chap. 7	CMOS Amplifiers
and hence
VGS , VTH		<		VDD , VR3 :							(7.125)
					Av		+ 1
				2
In other words,
W=L >				2ID						:	(7.126)
					Av		+ 2		2
	nCox		2VDD				, VR3
It follows that
	W=L > 172:5:										(7.127)

Exercise

Repeat the above example for Av = 10.

7.4 Source Follower

The MOS counterpart of the emitter follower is called the “source follower” (or the “commondrain” stage) and shown in Fig. 7.28. The amplifier senses the input at the gate and produces the output at the source, with the drain tied to VDD. The circuit's behavior is similar to that of the bipolar counterpart.

	VDD
Vin	M 1
Input Applied	Vout
to Gate	RL	Output Sensed
		at Source

Figure 7.28 Source follower.

7.4.1 Source Follower Core

If the gate voltage of M1 in Fig. 7.28 is raised by a small amount, Vin, the gate-source voltage tends to increase, thereby raising the source current and hence the output voltage. Thus, Vout “follows” Vin. Since the dc level of Vout is lower than that of Vin by VGS, we say the follower can serve as a “level shift” circuit. From our analysis of emitter followers in Chapter 5, we expect this topology to exhibit a subunity gain, too.

Figure 7.29(a) depicts the small-signal equivalent of the source follower, including channellength modulation. Recognizing that rO appears in parallel with RL, we have

gmv1(rOjjRL) = vout:

(7.128)

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	347 (1)

Sec. 7.4	Source Follower				347
					1
	v in	v 1	gmv 1	r O	g m
					v out
			v out	v in	RL r O
			RL
			(a)		(b)

Figure 7.29 (a) Small-signal equivalent of source follower, (b) simplified circuit.

Also,
vin = v1 + vout:					(7.129)
It follows that
vout =		gm(rOjjRL)			(7.130)
vin	1 + gm(rOjjRL)
=		rOjjRL		:	(7.131)
	1		+ rOjjRL
		gm

The voltage gain is therefore positive and less than unity. It is desirable to maximize RL (and

rO).

As with emitter followers, we can view the above result as voltage division between a resistance equal to 1=gm and another equal to rOjjRL [Fig. 7.29(b)]. Note, however, that a resistance placed in series with the gate does not affect (7.131) (at low frequencies) because it sustains a zero drop.

Example 7.16

A source follower is realized as shown in Fig. 7.30(a), where M2 serves as a current source. Calculate the voltage gain of the circuit.

	VDD
Vin	M 1	Vin	M 1	r O1
	Vout			Vout
Vb	M 2			r O2
	(a)		(b)

Figure 7.30 (a) Follower with ideal current source, (b) simplified circuit.

Solution

Since M2 simply presents an impedance of rO2 from the output node to ac ground [Fig. 7.30(b)], we substitute RL = rO2 in Eq. (7.131):

Av =		rO1jjrO2		:	(7.132)
	1		+ rO1jjrO2
		gm1

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	348 (1)

348	Chap. 7 CMOS Amplifiers

If rO1jjrO2 1=gm1, then Av 1.

Exercise

Repeat the above example if a resistance of value RS is placed in series with the source of

M2.

Example 7.17

Design a source follower to drive a 50load with a voltage gain of 0.5 and a power budget of 10 mW. Assume nCox = 100 A=V2, VTH = 0:5 V, = 0, and VDD = 1:8 V.

Solution

With RL = 50 and rO = 1 in Fig. 7.28, we have

	Av =					RL		(7.133)
		1				+ RL
				gm
	and hence
	gm	=				1	:	(7.134)
					50

The power budget and supply voltage yield a maximum supply current of 5.56 mA. Using this value for ID in gm = p2 nCox(W=L)ID gives

W=L = 360:

(7.135)

Exercise

What voltage gain can be achieved if the power budget is raised to 15 mW?

It is instructive to compute the output impedance of the source follower.2 As illustrated in Fig. 7.31, Rout consists of the resistance seen looking up into the source in parallel with that seen looking down into RL. With =6 0, the former is equal to (1=gm)jjrO, yielding

Rout =	1	jjrOjjRL	(7.136)
	gm
	1	jjRL:	(7.137)
	gm

In summary, the source follower exhibits a very high input impedance and a relatively low output impedance, thereby providing buffering capability.

2The input impedance is infinite at low frequencies.

BR	Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006]	June 30, 2007 at 13:42	349 (1)

Sec. 7.4

Source Follower

349

	r O		r O
M 1			M 1
			1	r O
RL			g m
		R out
			RL

Figure 7.31 Output resistance of source follower.

7.4.2 Source Follower With Biasing

The biasing of source followers is similar to that of emitter followers (Chapter 5). Figure 7.32 depicts an example where RG establishes a dc voltage equal to VDD at the gate of M1 (why?) and RS sets the drain bias current. Note that M1 operates in saturation because the gate and drain voltages are equal. Also, the input impedance of the circuit has dropped from infinity to RG.

	VDD
	R G
Vin	C1
	M 1	C2
		Vout
	RS

Figure 7.32 Source follower with input and output coupling capacitors.

Let us compute the bias current of the circuit. With a zero voltage drop across RG, we have

VGS + IDRS = VDD:

(7.138)

Neglecting channel-length modulation, we write

ID =	1	nCox W	(VGS , VTH)2	(7.139)
	2	L
=	1	nCox W	(VDD , IDRS , VTH)2:	(7.140)
	2	L

The resulting quadratic equation can be solved to obtain ID.

Example 7.18

Design the source follower of Fig. 7.32 for a drain current of 1 mA and a voltage gain of 0.8. Assume nCox = 100 A=V2, VTH = 0:5 V, = 0, VDD = 1:8 V, and RG = 50 k .

Solution

The unknowns in this problem are VGS, W=L, and RS. The following three equations can be formed:

ID =	1	nCox W	(VGS , VTH)2	(7.141)
	2	L
IDRS + VGS = VDD				(7.142)

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350				Chap. 7	CMOS Amplifiers
Av =			RS	:	(7.143)
	1		+ RS
		gm

If gm is written as 2ID=(VGS , VTH), then (7.142) and (7.143) do not contain W=L and can be solved to determine VGS and RS. With the aid of (7.142), we write (7.143) as

	Av =	RS							(7.144)
		VGS , VTH + RS
		2ID
	=	2IDRS							(7.145)
		VGS , VTH + 2IDRS
	=	2IDRS					:		(7.146)
		VDD , VTH + IDRS
	Thus,
	RS = VDD , VTH			Av					(7.147)
		ID	2	, Av					(7.148)
	= 867 :
	and
	VGS = VDD , IDRS								(7.149)
	= VDD , (VDD , VTH)						Av		(7.150)
						2 , Av
	= 0:933 V:								(7.151)
	It follows from (7.141) that
		W = 107:							(7.152)
		L

Exercise

What voltage gain can be achieved if W=L cannot exceed 50?

Equation (7.140) reveals that the bias current of the source follower varies with the supply voltage. To avoid this effect, integrated circuits bias the follower by means of a current source (Fig. 7.33).

7.5 Summary and Additional Examples

In this chapter, we have studied three basic CMOS building blocks, namely, the common-source stage, the common-gate stage, and the source follower. As observed throughout the chapter, the small-signal behavior of these circuits is quite similar to that of their bipolar counterparts, with the exception of the high impedance seen at the gate terminal. We have noted that the biasing