109CHAPTER FOUR

Memory Technologies and Interfacing

Parametric Considerations

Timing parameters were discussed in detail in Chapter Three. However, there are several that are unique to memory devices. These include access time, cycle time, and, in the case of DRAM, refresh interval.

Figure 4-11 shows a timing diagram illustrating memory read cycle timing parameters. These access times include:

•TAA (address access time): Valid Address to valid data delay

•TOE (output enable access time): Output Enable (OE) to valid data delay

•TCE (chip enable access time): Chip Enable (CE) to valid data delay

Chip

Enable

TCE

Output

Enable

TOE

Address

TAA

Data

Figure 4-11: Memory read cycle timing parameters.

Figure 4-12 shows a timing diagram illustrating memory write cycle timing parameters. The pulse width, setup, and hold times include:

•TWP: Write pulse width

•TAS: Address setup time

•TAH: Address hold time

•TDS: Data setup time

•TDH: Data hold time

Chip

Enable

TCE

TWP

Write

Enable

TAH

TAS

Address

TDS

Data

Floating

TDH

Figure 4-12: Memory write cycle timing parameters.

110EMBEDDED CONTROLLER

Hardware Design

In addition to the memory timing specs shown above, some memories, such as DRAM, have additional constraints as follows:

Cycle times

TRC (read cycle time): how closely read cycles can be spaced

TWC (write cycle time): how closely write cycles can be spaced

Read-modify-write cycle time is a special combined read/write cycle to the same address (e.g. increment a memory location)

DRAM Refresh Cycle

TREF: the maximum time between refresh/read/write cycles before DRAM data loss can occur

One of the DC characteristics of interest in an embedded system is the power consumption, particularly in a battery-operated design. Most static memories have low power or power-down modes activated by disabling the chip select or chip enable line. True CMOS SRAMs have typical power down supply currents in the low or sub-microampere range, allowing their data to be maintained using a battery while the main power is off as in an NVRAM. Some SRAMs are advertised as CMOS, even though they have some NMOS circuits internally to improve speed. These “mixed MOS” designs draw significantly more power and are not usually appropriate for typical battery operated applications.

Practical examples of actual memory specifications used in design of an embedded system can be found in Chapter Six.

Asynchronous vs. Synchronous Memory

An asynchronous memory is one that does not require any clock signals and delivers its output with a delay of one access time (the internal memory logic propagation time) after the address and control lines stabilize. Most SRAMs, like the SRAM described above, are asynchronous, but a few are synchronous and have clocks for internal latches to store the address and write enable signals. DRAMs are synchronous because they require RAS and CAS strobes to load the internal data latches. Generally asynchronous parts are easier to design with because of simpler timing constraints and direct compatibility with most processor buses.