Chapter 1

Introduction

This chapter introduces the ARM PrimeCell Synchronous Serial Port Master and Slave (PL021) and contains the following sections:

•About the ARM PrimeCell SSPMS (PL021) on page 1-2

•AMBA compatibility on page 1-5.

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1-1

Introduction

1.1About the ARM PrimeCell SSPMS (PL021)

The PrimeCell Synchronous Serial Port Master and Slave (SSPMS) is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB). The PrimeCell SSPMS is an AMBA compliant System-on-a- Chip peripheral that is developed, tested and licensed by ARM.

The PrimeCell SSPMS is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

•a Motorola SPI-compatible interface

•a Texas Instruments Synchronous Serial Interface

•a National Semiconductor Microwire interface.

In both master and slave configurations, the PrimeCell SSPMS performs:

•parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location deep transmit FIFO

•serial-to-parallel conversion on received data, buffering it in a similar 16-bit wide, 8-location deep receive FIFO.

Interrupts are generated to request servicing of the transmit and receive FIFO. An additional interrupt is provided which is raised when the receive FIFO over-runs.

The features of the PrimeCell SSPMS are covered under the following headings:

•Features of the PrimeCell SSPMS

•SPI features on page 1-3

•Microwire features on page 1-4

•Texas Instruments synchronous serial interface features on page 1-4.

1.1.1Features of the PrimeCell SSPMS

The PrimeCell SSPMS has the following features:

•compliance to the AMBA Specification (Rev 2.0) for easy integration into System-on-a-Chip (SoC) implementation

•master or slave operation

•programmable clock bit rate and prescale

•separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8 locations deep

•programmable choice of interface operation, SPI, Microwire or TI synchronous serial

1-2

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ARM DDI 0171B

Introduction

•programmable data frame size from 4 to 16 bits

•independent masking of transmit FIFO, receive FIFO and receive overrun interrupts

•internal loopback test mode available.

Figure 1-1 shows a block diagram of the PrimeCell SSPMS.

BnRES		PWDATAIn [15:0]		TxFRdDataIn [15:0]			SSPOE
PSEL			Tx FIFO		TX/RX params
			16 bits wide,				SSPTXD
PENABLE			8 locations
		PCLK	deep	SSPTXINTR			SFRMOUT
PWRITE						Transmit/	SCLKOUT
					SSPCLKDIV
	AMBA					receive
PADDRH [7:6]							SSPCTLOE
	APB					logic
					SSPCLK
	interface
PADDRL [4:2]		RxFRdData		RxWrData			SCLKIN
		[15:0]		[15:0]
PWDATA [15:0]			Rx FIFO				SFRMIN
PRDATA [15:0]			16 bits wide,	SSPRXINTR
			8 locations				SSPRXD
PCLK		PCLK	deep	SSPRORINTR
							SSPTXINTR
							SSPRXINTR
							SSPRORINTR
					PCLK
SSPCLK
PCLK		SSPCLK		TX/RX params	SSPTXINTR	Interrupt
							SSPINTR
						generator
	Register		Clock		SSPRXINTR
	block		prescaler
nSSPRST				SSPCLKDIV	SSPRORINTR

Figure 1-1 PrimeCell SSPMS block diagram

Note

For clarity, test logic is not represented in Figure 1-1.

1.1.2SPI features

The features of the Motorola SPI-compatible interface are:

•full duplex, four-wire synchronous transfers

•programmable clock polarity and phase.

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1-3

Introduction

1.1.3Microwire features

The features of the National Semiconductor Microwire interface are:

•half duplex transfer using 8-bit control message.

1.1.4Texas Instruments synchronous serial interface features

The features of the Texas Instruments synchronous serial interface are:

•full duplex, four-wire synchronous transfer

•transmit data pin tristateable when not transmitting.

1-4

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ARM DDI 0171B