- •Contents
- •Preface
- •About this document
- •Further reading
- •Feedback
- •Introduction
- •1.1 About the ARM PrimeCell Vectored Interrupt Controller (PL190)
- •Functional Overview
- •2.1 ARM PrimeCell Vectored Interrupt Controller (PL190) overview
- •2.2 PrimeCell VIC operation
- •2.3 PrimeCell VIC connectivity
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Summary of PrimeCell VIC registers
- •3.3 Register descriptions
- •3.4 Interrupt latency
- •3.5 Interrupt priority
Chapter 1
Introduction
This chapter introduces the ARM PrimeCell Vectored Interrupt Controller (PL190) and contains the following section:
•About the ARM PrimeCell Vectored Interrupt Controller (PL190) on page 1-2.
ARM DDI 0181C |
Copyright © 2000 ARM Limited. All rights reserved. |
1-1 |
Introduction
1.1About the ARM PrimeCell Vectored Interrupt Controller (PL190)
The PrimeCell Vectored Interrupt Controller (VIC) is an Advanced Microcontroller Bus Architecture (AMBA) compliant, System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM.
The PrimeCell VIC provides an interface to the interrupt system, and improves interrupt latency in two ways:
•moves the interrupt controller to the AMBA AHB bus
•provides vectored interrupt support for high-priority interrupt sources.
1.1.1Features of the PrimeCell VIC
The PrimeCell VIC has the following features:
•compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into System-on-Chip (SoC) implementation
•support for 32 standard interrupts
•support for 16 vectored IRQ interrupts
•hardware interrupt priority
•IRQ and FIQ generation
•AHB mapped for faster interrupt response
•software interrupt generation
•test registers
•raw interrupt status
•interrupt request status
•interrupt masking
•privileged mode support
•vector interrupt controller daisy chaining support.
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Copyright © 2000 ARM Limited. All rights reserved. |
ARM DDI 0181C |