Atmel Corporation
ARM7TDMITM (Thumb® )
Datasheet
January 1999
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is the registered trademark of Atmel Corporation, |
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Document Details
Title: ARM7TDMI (Thumb) Data Sheet
Literature Number: 0673B
Revision: B
Date: January 1999
Printed and distributed by Atmel ES2 in accordance with the license agreement existing between ARM for the ARM7TDMI microprocessor.
Revision History
Revision A: July 1996
Revision B: Reformatting of Revision A (numbering removed) and electrical characteristics removed. From now on, please see one of the following datasheets for electrical characteristics:
•ARM7TDMI Embedded Core ATC50 Electrical Characteristics (0.5 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V ± 0.3V)
•ARM7TDMI Embedded Core ATC50/E2 Electrical Characteristics (0.5 micron three-layer-metal CMOS/ NVM process intended for use with a supply voltage of 3.3V ± 0.3V)
•ARM7TDMI Embedded Core ATC35 Electrical Characteristics (0.35 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V ± 0.3V)
© Copyright Advanced RISC Machines Limited (ARM) 1996
ARM, Thumb and ARM Powered are registered trademarks of ARM Limited.
The ARM7TDMI EmbeddedICE, BlackICE and ICEbreaker are trademarks of ARM Ltd.
Neither the whole nor any part of the information contained in, or the product described in, this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this datasheet is subject to continuous developments and improvements. All particulars of the product and its use contained in this datasheet are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose are excluded.
This datasheet is intended only to assist the reader in the use of the product. ARM Ltd. shall not be liable for any loss or damage arising from the use of any information in this datasheet, or any error or omission in such information, or any incorrect use of the product.
Important Notice
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.
Marks bearing ®and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others.
Atmel ES2
Zone Industrielle
13106 Rousset Cedex
France
Tel: (+33) (0)4 42 53 60 00
Fax: (+33) (0)4 42 53 60 01
For other Atmel addresses see back page.
Table of Contents
Architectural Overview ....................................................................................................................... |
1 |
Introduction ..................................................................................................................... |
1 |
ARM7TDMI Architecture ................................................................................................. |
2 |
ARM7TDMI Block Diagram ............................................................................................. |
3 |
ARM7TDMI Core Diagram .............................................................................................. |
4 |
ARM7TDMI Functional Diagram ..................................................................................... |
5 |
Signal Description .............................................................................................................................. |
7 |
Programmer’s Model ........................................................................................................................ |
15 |
Processor Operating States .......................................................................................... |
15 |
Switching State ............................................................................................................. |
15 |
Memory Formats ........................................................................................................... |
16 |
Instruction Length .......................................................................................................... |
17 |
Data Types .................................................................................................................... |
17 |
Operating Modes ........................................................................................................... |
17 |
Registers ....................................................................................................................... |
17 |
The Program Status Registers ...................................................................................... |
21 |
Exceptions ..................................................................................................................... |
23 |
Interrupt Latencies ........................................................................................................ |
26 |
Reset ............................................................................................................................. |
26 |
ARM Instruction Set ......................................................................................................................... |
27 |
Instruction Set Summary ............................................................................................... |
28 |
The Condition Field ....................................................................................................... |
30 |
Branch and Exchange (BX) ........................................................................................... |
30 |
Branch and Branch with Link (B, BL) ............................................................................ |
32 |
Data Processing ............................................................................................................ |
34 |
PSR Transfer (MRS, MSR) ........................................................................................... |
40 |
Multiply and Multiply-Accumulate (MUL, MLA) ............................................................. |
44 |
Multiply Long and Multiply-Accumulate Long (MULL,MLAL) ........................................ |
46 |
Single Data Transfer (LDR, STR) ................................................................................. |
48 |
Halfword and Signed Data Transfer(LDRH/STRH/LDRSB/LDRSH) ............................. |
52 |
Block Data Transfer (LDM, STM) .................................................................................. |
56 |
Single Data Swap (SWP) .............................................................................................. |
62 |
Software Interrupt (SWI) ............................................................................................... |
64 |
Coprocessor Data Operations (CDP) ............................................................................ |
66 |
Coprocessor Data Transfers (LDC, STC) ..................................................................... |
68 |
Coprocessor Register Transfers (MRC, MCR) ............................................................. |
70 |
Undefined Instruction .................................................................................................... |
71 |
Instruction Set Examples .............................................................................................. |
72 |
Thumb Instruction Set ...................................................................................................................... |
77 |
Format Summary .......................................................................................................... |
78 |
Opcode Summary ......................................................................................................... |
79 |
|
i |
Format 1: move shifted register .................................................................................... |
80 |
Format 2: add/subtract .................................................................................................. |
81 |
Format 3: move/compare/add/subtract immediate ........................................................ |
83 |
Format 4: ALU operations ............................................................................................. |
84 |
Format 5: Hi register operations/branch exchange ....................................................... |
86 |
Format 6: PC-relative load ............................................................................................ |
89 |
Format 7: load/store with register offset ........................................................................ |
90 |
Format 8: load/store sign-extended byte/halfword ........................................................ |
92 |
Format 9: load/store with immediate offset ................................................................... |
94 |
Format 10: load/store halfword ..................................................................................... |
96 |
Format 11: SP-relative load/store ................................................................................. |
98 |
Format 12: load address ............................................................................................. |
100 |
Format 13: add offset to Stack Pointer ........................................................................ |
101 |
Format 14: push/pop registers .................................................................................... |
102 |
Format 15: multiple load/store ..................................................................................... |
104 |
Format 16: conditional branch ..................................................................................... |
105 |
Format 17: software interrupt ...................................................................................... |
107 |
Format 18: unconditional branch ................................................................................. |
108 |
Format 19: long branch with link ................................................................................. |
109 |
Instruction Set Examples ............................................................................................ |
110 |
Memory Interface ............................................................................................................................ |
117 |
Overview ..................................................................................................................... |
117 |
Cycle Types ................................................................................................................ |
118 |
Data Transfer Size ...................................................................................................... |
124 |
Instruction Fetch .......................................................................................................... |
124 |
Memory Management ................................................................................................. |
126 |
Locked Operations ...................................................................................................... |
126 |
Stretching Access Times ............................................................................................. |
126 |
The ARM Data Bus ..................................................................................................... |
127 |
The External Data Bus ................................................................................................ |
129 |
Coprocessor Interface .................................................................................................................... |
135 |
Overview ..................................................................................................................... |
135 |
Interface Signals ......................................................................................................... |
136 |
Register Transfer Cycle .............................................................................................. |
137 |
Privileged Instructions ................................................................................................. |
137 |
Idempotency ................................................................................................................ |
137 |
Undefined Instructions ................................................................................................ |
137 |
Debug Interface ............................................................................................................................... |
139 |
Overview ..................................................................................................................... |
139 |
Debug Systems ........................................................................................................... |
140 |
Debug Interface Signals .............................................................................................. |
141 |
ii Table of Contents 
Table of Contents
Scan Chains and JTAG Interface ................................................................................ |
143 |
Reset ........................................................................................................................... |
145 |
Pullup Resistors .......................................................................................................... |
145 |
Instruction Register ..................................................................................................... |
145 |
Public Instructions ....................................................................................................... |
145 |
Test Data Registers .................................................................................................... |
147 |
ARM7TDMI Core Clocks ............................................................................................. |
151 |
Determining the Core and System State ..................................................................... |
152 |
The PC’s Behaviour During Debug ............................................................................. |
155 |
Priorities / Exceptions .................................................................................................. |
157 |
Scan Interface Timing ................................................................................................. |
158 |
Debug Timing .............................................................................................................. |
161 |
ICEBreaker Module ......................................................................................................................... |
163 |
Overview ..................................................................................................................... |
164 |
The Watchpoint Registers ........................................................................................... |
165 |
Programming Breakpoints ........................................................................................... |
168 |
Programming Watchpoints .......................................................................................... |
169 |
The Debug Control Register ....................................................................................... |
169 |
Debug Status Register ................................................................................................ |
170 |
Coupling Breakpoints and Watchpoints ...................................................................... |
171 |
Disabling ICEBreaker .................................................................................................. |
172 |
ICEBreaker Timing ...................................................................................................... |
172 |
Programming Restriction ............................................................................................. |
172 |
Debug Communications Channel ............................................................................... |
173 |
Instruction Cycle Operations ......................................................................................................... |
175 |
Introduction ................................................................................................................. |
176 |
Branch and Branch with Link ...................................................................................... |
176 |
THUMB Branch with Link ............................................................................................ |
177 |
Branch and Exchange (BX) ......................................................................................... |
177 |
Data Operations .......................................................................................................... |
178 |
Multiply and Multiply Accumulate ................................................................................ |
179 |
Load Register .............................................................................................................. |
180 |
Store Register ............................................................................................................. |
180 |
Load Multiple Registers ............................................................................................... |
181 |
Store Multiple Registers .............................................................................................. |
182 |
Data Swap ................................................................................................................... |
182 |
Software Interrupt and Exception Entry ...................................................................... |
183 |
Coprocessor Data Operation ...................................................................................... |
183 |
Coprocessor Data Transfer (from memory to coprocessor) ........................................ |
184 |
Coprocessor Data Transfer (from coprocessor to memory) ........................................ |
185 |
Coprocessor Register Transfer (Load from coprocessor) ........................................... |
186 |
Coprocessor Register Transfer (Store to coprocessor) .............................................. |
186 |
|
iii |
Undefined Instructions and Coprocessor Absent ........................................................ |
187 |
Unexecuted Instructions .............................................................................................. |
187 |
Instruction Speed Summary ........................................................................................ |
188 |
AC/DC Parameters .......................................................................................................................... |
189 |
Timing Diagrams ......................................................................................................... |
190 |
iv Table of Contents 
This chapter introduces the ARM7TDMI architecture and shows block, core, and functional diagrams for the ARM7TDMI.
Introduction
The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance for very low power consumption and price.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM memory interface has been designed to allow the performance potential to be realised without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs.
Architectural |
Overview |
Rev. 0673B–12/98 |
1 |