CY7C68013

3.16Autopointer Access

FX2 provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment a pointer address after every memory access. This capability is available to and from both internal and external RAM. The autopointers are available in external FX2 registers, under control of a mode bit (AUTOPTRSETUP.0). Using the external FX2 autopointer access (at 0xE67B – 0xE67C) allows the autopointer to access all RAM, internal and external to the part. Also, the autopointers can point to any FX2 register or endpoint buffer space. When autopointer access to external memory is enabled, location 0xE67B and 0xE67C in XDATA and PDATA space cannot be used.

3.17I2C-compatible Controller

FX2 has one I2C-compatible port that is driven by two internal controllers, one that automatically operates at boot time to load VID/PID/DID and configuration information, and another that the 8051, once running, uses to control external I2C- compatible devices. The I2C-compatible port operates in master mode only.

3.17.1I2C-compatible Port Pins

The I2C-compatible pins SCL and SDA must have external 2.2-kΩ pull-up resistors. External EEPROM device address pins must be configured properly. See Table 3-7 for configuring the device address pins.

Table 3-7. Strap Boot EEPROM Address Lines to These Values

Bytes	Example EEPROM	A2	A1	A0
16	24LC00[4]	N/A	N/A	N/A
128	24LC01	0	0	0
256	24LC02	0	0	0
4K	24LC32	0	0	1
8K	24LC64	0	0	1

Note:

4.This EEPROM does not have address pins.

3.17.2I2C-compatible Interface Boot Load Access

At power-on reset the I2C-compatible interface boot loader will load the VID/PID/DID/a configuration byte and up to eight kbytes of program/data. The available RAM spaces are eight kbytes from 0x0000–0x1FFF and 512 bytes from 0xE000–0xE1FF. The 8051 will be in reset. I2C-compatible interface boot loads only occur after power-on reset.

3.17.3I2C-compatible Interface General Purpose Access

The 8051 can control peripherals connected to the I2C- compatible bus using the I2CTL and I2DAT registers. FX2 provides I2C compatible master control only, it is never an I2C- compatible slave.

4.0Pin Assignments

Figure 4-1 identifies all signals for the four package types. The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128-, 100-, and 56-pin packages.

The 56-pin package is the lowest-cost version. The signals on the left edge of the 56-pin package in Figure 4-1 are common to all versions in the FX2 family. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power-on default configuration.

The 100-pin package adds functionality to the 56-pin package by adding these pins:

•PORTC or alternate GPIFADR[7...0] address signals

•PORTE or alternate GPIFADR8 address signals and 7 more 8051 signals

•Three GPIF Control signals

•Four GPIF Ready signals

•Nine 8051 signals (two USARTs, three timer inputs, INT4,and INT5#)

•BKPT, RD#, WR#

The 128-pin package is the full version, adding the 8051 address and data buses plus control signals. Note that two of the required signals, RD# and WR#, are present in the 100-pin version. In the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC.

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CY7C68013

Port

GPIF Master

Slave FIFO

PD7

FD[15]

FD[15]

PD6

FD[14]

FD[14]

PD5

FD[13]

FD[13]

PD4

FD[12]

FD[12]

PD3

FD[11]

FD[11]

PD2

FD[10]

FD[10]

PD1

FD[9]

FD[9]

PD0

FD[8]

FD[8]

PB7

FD[7]

FD[7]

PB6

FD[6]

FD[6]

PB5

FD[5]

FD[5]

PB4

FD[4]

FD[4]

PB3

FD[3]

FD[3]

PB2

FD[2]

FD[2]

PB1

FD[1]

FD[1]

56

PB0

FD[0]

FD[0]

XTALIN

RDY0

SLRD

XTALOUT

RDY1

SLWR

RESET#

WAKEUP#

CTL0

FLAGA

SCL

CTL1

FLAGB

SDA

INT0#/PA0

CTL2

FLAGC

INT0#/PA0

INT0#/ PA0

IFCLK

INT1#/PA1

INT1#/PA1

INT1#/ PA1

CLKOUT

PA2

PA2

SLOE

WU2/PA3

WU2/PA3

WU2/PA3

DPLUS

PA4

PA4

FIFOADR0

DMINUS

PA5

PA5

FIFOADR1

PA6

PA6

PKTEND

PA7

PA7

PA7/FLAGD/SLCS#

CTL3

CTL4

CTL5

RDY2

RDY3

100 RDY4

RDY5

BKPT

	PORTC7/GPIFADR7
	PORTC6/GPIFADR6
	PORTC5/GPIFADR5
	PORTC4/GPIFADR4					RxD0
	PORTC3/GPIFADR3						TxD0
	PORTC2/GPIFADR2					RxD1
	PORTC1/GPIFADR1						TxD1
	PORTC0/GPIFADR0
							INT4
	PE7/GPIFADR8					INT5#
				TIMER2
	PE6/T2EX
				TIMER1
	PE5/INT6
	PE4/RxD1OUT			TIMER0
	PE3/RxD0OUT
	PE2/T2OUT
								RD#
	PE1/T1OUT
	PE0/T0OUT						WR#
	D7							CS#
	D6							OE#
	D5				PSEN#
	D4
	D3							A15
	D2							A14
	D1
								A13
	D0
								A12
								A11
	128							A10
									A9
									A8
									A7

		A6
		A5
	EA	A4
		A3
		A2
		A1
		A0

Figure 4-1. Signals

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CY7C68013

		128		127		126		125		124		123		122		121		120		119		118		117		116		115		114		113		112		111		110		109		108		107		106		105		104		103
		A10		A9		A8		GND		PD7/FD15		PD6/FD14		PD5/FD13		PD4/FD12		A7		A6		A5		A4		GND		PE7/GPIFADR8		PE6/T2EX		PE5/INT6		PE4/RXD1OUT		PE3/RXD0OUT		PE2/T2OUT		PE1/T1OUT		PE0/T0OUT		VCC		INT5#		PD3/FD11		PD2/FD10		PD1/FD9
	GND																																																					VCC
1	CLKOUT																																																					PD0/FD8
2	VCC																																																					*WAKEUP
3
	RDY0/*SLRD																																																					RESET#
4
	RDY1/*SLWR
5																																																						CTL5
	RDY2
6																																																						A3
	RDY3
7																																																						A2
	RDY4
8																																																						A1
	RDY5
9																																																						A0
	AVCC
10																																																						GND
	XTALOUT
11																																														PA7/*FLAGD/SLCS#
12	XTALIN																																																	PA6/*PKTEND
13	AGND																																																	PA5/FIFOADR1
	NC
14																																																		PA4/FIFOADR0
	NC
15																																																						D7
	NC
16																																																						D6
	VCC																																																					D5
17
	DPLUS																			CY7C68013
18																																																						PA3/*WU2
19	DMINUS																			128-pin TQFP																																PA2/*SLOE
	GND
20																																																						PA1/INT1#
	A11
21																																																						PA0/INT0#
22	A12																																																					VCC
	A13																																																					GND
23
	A14
24																																																		PC7/GPIFADR7
25	A15																																																	PC6/GPIFADR6
	VCC
26																																																		PC5/GPIFADR5
	GND
27																																																		PC4/GPIFADR4
	INT4
28																																																		PC3/GPIFADR3
29	T0																																																	PC2/GPIFADR2
30	T1																																																	PC1/GPIFADR1
	T2
31																																																		PC0/GPIFADR0
	IFCLK
32																																																			CTL2/*FLAGC
33	RESERVED																																																		CTL1/*FLAGB
34	BKPT																																																		CTL0/*FLAGA
35	EA																																																					VCC
	SCL
36																																																						CTL4
	SDA
37																																																						CTL3
	OE#
38																																																						GND
		PSEN#		RD#		WR#		CS#		VCC		PB0/FD0		PB1/FD1		PB2/FD2		PB3/FD3		VCC		GND		TxD0		RxD0		TxD1		RxD1		PB4/FD4		PB5/FD5		PB6/FD6		PB7/FD7		GND		D0		D1		D2		D3		D4		VCC
		39		40		41		42		43		44		45		46		47		48		49		50		51		52		53		54		55		56		57		58		59		60		61		62		63		64

Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment

* denotes programmable polarity

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

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CY7C68013

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

CLKOUT

GND

PD7/FD15

PD6/FD14

PD5/FD13

PD4/FD12

GND

PE7/GPIFADR8

PE6/T2EX

PE5/INT6

PE4/RXD1OUT

PE3/RXD0OUT

PE2/T2OUT

PE1/T1OUT

PE0/T0OUT

VCC

INT5#

PD3/FD11

PD2/FD10

PD1/FD9

VCC

PD0/FD8

1

GND

*WAKEUP

2

RDY0/*SLRD

VCC

3

RDY1/*SLWR

RESET#

4

RDY2

CTL5

5

RDY3

GND

6

RDY4

PA7/*FLAGD/SLCS#

7

RDY5

PA6/*PKTEND

8

AVCC

PA5/FIFOADR1

9

XTALOUT

PA4/FIFOADR0

10

XTALIN

PA3/*WU2

11

AGND

PA2/*SLOE

12

NC

PA1/INT1#

13

NC

PA0/INT0#

14

CY7C68013

NC

VCC

15

VCC

100-pin TQFP

GND

16

DPLUS

PC7/GPIFADR7

17

DMINUS

PC6/GPIFADR6

18

GND

PC5/GPIFADR5

19

VCC

PC4/GPIFADR4

20

GND

PC3/GPIFADR3

21

INT4

PC2/GPIFADR2

22

T0

PC1/GPIFADR1

23

T1

PC0/GPIFADR0

24

T2

CTL2/*FLAGC

25

IFCLK

CTL1/*FLAGB

26

RESERVED

CTL0/*FLAGA

27

BKPT

VCC

28

SCL

CTL4

29

SDA

CTL3

30

	RD#		WR#		VCC		PB0/FD0		PB1/FD1		PB2/FD2		PB3/FD3		VCC		GND		TxD0		RxD0		TxD1		RxD1		PB4/FD4		PB5/FD5		PB6/FD6		PB7/FD7		GND		VCC		GND
	31		32		33		34		35		36		37		38		39		40		41		42		43		44		45		46		47		48		49		50

Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment

* denotes programmable polarity

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

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CY7C68013

CY7C68013

56-pin SSOP

	PD5/FD13		PD4/FD12
1				56
	PD6/FD14		PD3/FD11
2				55
	PD7/FD15		PD2/FD10
3				54
	GND		PD1/FD9
4				53
	CLKOUT		PD0/FD8
5				52
	VCC		*WAKEUP
6				51
	GND		VCC
7				50
	RDY0/*SLRD		RESET#
8				49
	RDY1/*SLWR		GND
9				48
	AVCC	PA7/*FLAGD/SLCS#
10				47
	XTALOUT		PA6/PKTEND
11				46
	XTALIN		PA5/FIFOADR1
12				45
	AGND		PA4/FIFOADR0
13				44
	VCC		PA3/*WU2
14				43
	DPLUS		PA2/*SLOE
15				42
	DMINUS		PA1/INT1#
16				41
	GND		PA0/INT0#
17				40
	VCC		VCC
18				39
	GND		CTL2/*FLAGC
19				38
	IFCLK		CTL1/*FLAGB
20				37
	RESERVED		CTL0/*FLAGA
21				36
	SCL		GND
22				35
	SDA		VCC
23				34
	VCC		GND
24				33
25	PB0/FD0		PB7/FD7	32
	PB1/FD1		PB6/FD6
26				31
	PB2/FD2		PB5/FD5
27				30
	PB3/FD3		PB4/FD4
28				29

Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment

* denotes programmable polarity

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CY7C68013

RDY0/*SLRD 1

RDY1/*SLWR 2

AVCC 3

XTALOUT 4

XTALIN 5

AGND 6

VCC 7

DPLUS 8

DMINUS 9

GND 10

VCC 11

GND 12

*IFCLK 13

RESERVED 14

GND		VCC		CLKOUT		GND		PD7/FD15		PD6/FD14		PD5/FD13		PD4/FD12		PD3/FD11		PD2/FD10		PD1/FD9		PD0/FD8		*WAKEUP		VCC
56		55		54		53		52		51		50		49		48		47		46		45		44		43

CY7C68013

56-pin QFN

15		16		17		18		19		20		21		22		23		24		25		26		27		28
SCL		SDA		VCC		PB0/FD0		PB1/FD1		PB2/FD2		PB3/FD3		PB4/FD4		PB5/FD5		PB6/FD6		PB7/FD7		GND		VCC		GND

42 RESET#

41 GND

40 PA7/*FLAGD/SLCS#

39 PA6/*PKTEND

38 PA5/FIFOADR1

37 PA4/FIFOADR0

36 PA3/*WU2

35 PA2/*SLOE

34 PA1/INT1#

33 PA0/INT0#

32 VCC

31 CTL2/*FLAGC

30 CTL1/*FLAGB

29 CTL0/*FLAGA

Figure 4-5. CY7C68013 56-pin QFN Pin Assignment

* denotes programmable polarity

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