21. External Programming

This section describes how to program and verify Flash memory, EEPROM, lock bits, and fuse bits in ATtiny2313A/4313.

21.1Memory Parametrics

Flash memory parametrics are summarised in Table 21-1, below.

Table 21-1.	No. of Words in a Page and No. of Pages in the Flash
Device		Flash Size	Page Size	PCWORD(1)	Pages	PCPAGE	PCMSB
ATtiny2313A		1K word	16 words	PC[3:0]	64	PC[9:4]	9
		(2K bytes)
ATtiny4313		2K words	32 words	PC[4:0]	64	PC[10:5]	10
		(4K bytes)
Note: 1. See Table 19-1 on page 174.

EEPROM parametrics are summarised in Table 21-2, below.

Table 21-2.	No. of Words in a Page and No. of Pages in the EEPROM
		EEPROM		PCWORD(1)		PCPAGE(1)
Device		Size	Page Size		Pages		EEAMSB
ATtiny2313A		128 bytes	4 bytes	EEA[1:0]	32	EEA[6:2]	6
ATtiny4313		256 bytes	4 bytes	EEA[1:0]	64	EEA[7:2]	7

Note: 1. See Table 19-1 on page 174.

21.2Parallel Programming

Parallel programming signals and connections are illustrated in Figure 21-1, below.

Figure 21-1. Parallel Programming

+5V

RDY/BSY PD1

VCC

OE PD2

WR PD3

BS1/PAGEL PD4

XA0		PD5	PB7 - PB0		DATA I/O
XA1/BS2		PD6

+12 V RESET

XTAL1

GND

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Signals are described in Table 21-3, below. Pins not listed in the table are referenced by pin names.

Table 21-3.						Pin and Signal Names Used in Programming Mode
	Signal Name						Pin(s)	I/O	Function
									0: Device is busy programming,
	RDY/BSY						PD1	O
									1: Device is ready for new command.
							PD2	I	Output Enable (Active low).
	OE
							PD3	I	Write Pulse (Active low).
	WR
	BS1/PAGEL						PD4	I	Byte Select 1 (“0” selects low byte, “1” selects high byte).
									Program Memory and EEPROM Data Page Load.
	XA0						PD5	I	XTAL Action Bit 0
	XA1/BS2						PD6	I	XTAL Action Bit 1.
									Byte Select 2 (0: low byte, 1: 2nd high byte).
	DATA I/O						PB7-0	I/O	Bi-directional Data bus (Output when		is low).
										OE

Pulses are assumed to be at least 250 ns, unless otherwise noted.

Table 21-4. Pin Values Used to Enter Programming Mode

Pin	Symbol	Value
XA1	Prog_enable[3]	0
XA0	Prog_enable[2]	0
BS1	Prog_enable[1]	0
WR	Prog_enable[0]	0

Pins XA1 and XA0 determine the action when CLKI is given a positive pulse, as shown in Table 21-5.

Table 21-5. XA1 and XA0 Coding

XA1	XA0	Action when CLKI is Pulsed
0	0	Load Flash or EEPROM address (high or low address byte, determined by BS1)
0	1	Load data (high or low data byte for Flash, determined by BS1)
1	0	Load command
1	1	No action, idle

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When pulsing WR or OE, the command loaded determines the action executed. The different command options are shown in Table 21-6.

Table 21-6. Command Byte Bit Coding

Command Byte	Command
1000 0000	Chip Erase
0100 0000	Write fuse bits
0010 0000	Write lock bits
0001 0000	Write Flash
0001 0001	Write EEPROM
0000 1000	Read signature bytes and calibration byte
0000 0100	Read fuse and lock bits
0000 0010	Read Flash
0000 0011	Read EEPROM

21.2.1Enter Programming Mode

The following algorithm puts the device in Parallel (High-voltage) Programming mode:

1.Set Prog_enable pins listed in Table 21-4 on page 185 to “0000”, RESET pin and VCC to 0V.

2.Apply 4.5 - 5.5V between VCC and GND.

3.Ensure that VCC reaches at least 1.8V within the next 20 µs.

4.Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.

5.Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched.

6.Wait at least 300 µs before giving any parallel programming commands.

7.Exit Programming mode by power the device down or by bringing RESET pin to 0V.

If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be used.

1.Set Prog_enable pins listed in Table 21-4 on page 185 to “0000”, RESET pin to 0V and VCC to 0V.

2.Apply 4.5 - 5.5V between VCC and GND.

3.Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.

4.Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched.

5.Wait until VCC actually reaches 4.5 -5.5V before giving any parallel programming commands.

6.Exit Programming mode by power the device down or by bringing RESET pin to 0V.

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21.2.2Considerations for Efficient Programming

Loaded commands and addresses are retained in the device during programming. For efficient programming, the following should be considered.

•When writing or reading multiple memory locations, the command needs only be loaded once

•Do not write the data value 0xFF, since this already is the contents of the entire Flash and EEPROM (unless the EESAVE Fuse is programmed) after a Chip Erase

•Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This also applies to reading signature bytes

21.2.3Chip Erase

A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. The Chip Erase command will erase all Flash and EEPROM plus lock bits. If the EESAVE fuse is programmed, the EEPROM is not erased.

Lock bits are not reset until the program memory has been completely erased. Fuse bits are not changed.

The Chip Erase command is loaded as follows:

1.Set XA1, XA0 to “10”. This enables command loading.

2.Set BS1 to “0”.

3.Set DATA to “1000 0000”. This is the command for Chip Erase.

4.Give XTAL1 a positive pulse. This loads the command.

5.Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6.Wait until RDY/BSY goes high before loading a new command.

21.2.4Programming the Flash

Flash is organized in pages, as shown in Table 21-1 on page 184. When programming the Flash, the program data is first latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory:

A.Load Command “Write Flash”

1.Set XA1, XA0 to “10”. This enables command loading.

2.Set BS1 to “0”.

3.Set DATA to “0001 0000”. This is the command for Write Flash.

4.Give XTAL1 a positive pulse. This loads the command.

B.Load Address Low byte

1.Set XA1, XA0 to “00”. This enables address loading.

2.Set BS1 to “0”. This selects low address.

3.Set DATA = Address low byte (0x00 - 0xFF).

4.Give XTAL1 a positive pulse. This loads the address low byte.

C.Load Data Low Byte

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1.Set XA1, XA0 to “01”. This enables data loading.

2.Set DATA = Data low byte (0x00 - 0xFF).

3.Give XTAL1 a positive pulse. This loads the data byte.

D.Load Data High Byte

1.Set BS1 to “1”. This selects high data byte.

2.Set XA1, XA0 to “01”. This enables data loading.

3.Set DATA = Data high byte (0x00 - 0xFF).

4.Give XTAL1 a positive pulse. This loads the data byte.

E.Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 21-2 on page 189. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write.

F.Load Address High byte

1.Set XA1, XA0 to “00”. This enables address loading.

2.Set BS1 to “1”. This selects high address.

3.Set DATA = Address high byte (0x00 - 0xFF).

4.Give XTAL1 a positive pulse. This loads the address high byte.

G.Program Page

1.Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.

2.Wait until RDY/BSY goes high (See Figure 21-3 on page 189 for signal waveforms).

H.Repeat B through H until the entire Flash is programmed or until all data has been programmed.

I.End Page Programming

1.1. Set XA1, XA0 to “10”. This enables command loading.

2.Set DATA to “0000 0000”. This is the command for No Operation.

3.Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.

Flash page addressing is illustrated in Figure 21-2, below. Symbols used are described in Table 19-1 on page 174.

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