Allen and Holberg - CMOS Analog Circuit Design

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-14

SUMMARY OF CURRENT SINKS/SOURCES

Current Sink/Source

Simple

Cascode

High-Swing Cascode

Regulated Cascode

rOUT					Minimum Voltage
	rd s						VON
≈ gm2rds2rds1					VT + 2 VON
≈ gm2rds2rds1						2 VON
≈ g	m	2r	ds	3	V	T	+ 2 V	ON

Allen and Holberg - CMOS Analog Circuit Design

Page V.4-1

V.4 - CURRENT MIRRORS/AMPLIFIERS

What Is A Current Mirror/Amplifier ?

Rin				Rout
iI		CURRENT		iO
		MIRROR/
+		AMPLIFIER		+
vI				vO
-			-
Ideally,
iO = AI iI
Rin ≈ 0	Rout ≈ ∞
Graphical Characterization
iI	slope = 1/Rin		iO

II

slope = 1/Rout

IO

	vI	vO
	vMIN	vMIN
INPUT	iO	OUTPUT

AI

1

iI

TRANSFER

Allen and Holberg - CMOS Analog Circuit Design

Page V.4-2

CURRENT MIRROR AND CURRENT AMPLIFIERS

Sources of Errors

		i I		iO
CURRENT	iO	+		+
iI
MIRROR/		vDS1 M1	+	M2 vDS2
AMPLIFIER		-	vGS	-
			-

In general,

i

O

W

L

1

v

GS

- V

2

1+λv

µ

o2

C

2

T 2

1+λv

DS2

ox2

i

= W L

v - V

µ C

I

1

2

GS

o1

T 1

DS1

ox1

If the devices are matched,

iO		W2L1 1+λvDS2
i		= W L			1+λv
	I		1	2
						DS1

	If vDS1 = vDS2,
	iO	=	W	2 L 1
	iI		W1L2

Therefore the sources of error are:

1). vDS1 ≠ vDS2

2). M1 and M2 not matched (Δβ and VT)

Allen and Holberg - CMOS Analog Circuit Design

Page V.4-3

Simple Current Mirror With λ ≠ 0

Circuit -

iI

+M1

	vDS1	+
	-
		vGS
		-
		vSS

	iO		)x100%
			1
			-
	M2	+	DS1	DS2
			+ λv + λv
		vDS2
		-	1	1
			(
			Ratio Error

10

λ = 0.02

8

λ = 0.015

6
4
2				λ = 0.01
0
0V	1V	2V	3V	4V	5V

VDS1-VDS2

Ratio error (%) versus drain voltage difference -

Used to measure λ -

iO		1+ λ vD S 2 S1
i		= 1+ λ v		S
	I		D S 1
				2

If S1 = S2, vDS2 = 10V, vDS1 = 1V, and iO/iI = 1.501, then

iO	= 1.501 =	1+10λ	---> λ =	0.5	= 0.059
iI		1+ λ		8.5

Allen and Holberg - CMOS Analog Circuit Design Page V.4-4

Matching Accuracy of MOS Current Mirrors

Neglect

λ effects

iD1

iD2

β2(vGS2-VT2)2

i

O =

i

D2 =

β1(vGS1-VT1)2

M1

+

+

M2

iI

iD1

vGS1

vGS2

(vDS2 > vGS2 - VT1)

-

-

Define:

Δβ = β2 - β1

and

β =

β1 + β2

2

VT = VT2 - VT1

and

VT =

VT1+VT2

2

β

= β

-

Δβ

, β

= β

Δβ

, V

= V

-

VT

1

2

2

+

2

T1

T

2

and VT2 = VT +

VT

2

Thus,

2

Δβ

- v

-

VT 2

Δβ

1-

VT

iO

β+

2

v

GS

T

1 +

2(vGS-VT)

2

2β

iI

=

Δβ

- v

+

VT

2

=

β

VT

β-

v

2

1 -

1+

2(vGS-VT)

2

GS

T

2β

iO

≈

Δβ

Δβ

VT

VT

2

iI

1+

2β

1+

1-

1-

2β

2(vGS-VT)

2(vGS-VT)

iO

≈ 1 +

Δβ

2 VT

iI

β

- (vGS - VT),

Δβ

≈ ± 5% ,

VT

= ± 10%

β

(vGS - VT)

iO ≈ 1 ± 0.05 - (± 0.2) = 1 ± 0.15 iI

= 1 ± 0.25 if β and VT are correlated

Allen and Holberg - CMOS Analog Circuit Design

Page V.4-5

Matching Accuracy - Continued

Illustration

- 1)100%
O	I
i i
RATIO ERROR (

7

6

5

4

3

2

1

II = 1uA

II = 5uA

II = 10uA

II = 50uA

1	2	3	4	5	6	7	8	9	10
				VT(mV)

Allen and Holberg - CMOS Analog Circuit Design

Page V.4-6

Layout Techniques to Remove Layout Error

Layout without correction technique -

iI

iO

		iI	iO
M1	M2		M2
			VSS
	VSS		Layou
t with correction technique -
iI	i
	O

iI

iO

M1

M2

M2

M2

M2

M2

M2

M2

M2

M2

M2

M1

a

b

c

d

e

a

b

c

d

e

VSS

VSS

Allen and Holberg - CMOS Analog Circuit Design

Page V.4-7

Practical Current Mirrors/Amplifiers

•Simple mirror

•Cascode current mirror

•Wilson current mirror

Simple Current Mirror -

60uA

40uA

iOUT

20uA

0

iI = 60uA

iI = 50uA

iI = 40uA

iI = 30uA

iI = 20uA

iI = 10uA

Current mirrors and amplifiers

.MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6

M1 1 1 0 0 MNMOS1 W=3U L=3U

M2 3 1 0 0 MNMOS1 W=3U L=3U IIN 0 1

VOUT 3 0

.DC VOUT 0 5 0.1 +IIN 0 60U 10U

.PRINT DC ID(M2)

.PROBE

.END

0	1	2	3	4	5
			vOUT

iI		iO
3u	3u	+
3u	3u
M1	M2	vO
		-

Allen and Holberg - CMOS Analog Circuit Design Page V.4-8

Cadcode Current Mirror

CIRCUIT

SPICE

mproved current mirror

iI

iOUT

60uA

.MODEL MNMOS1 NMOS VTO=0.75 KP=25U

= 60uA

M1 1 1 0 0 MNMOS1 W=3U L=3U

iI

+LAMBDA=0.01 GAMMA=0.8 PHI=0.6

M2 2 1 0 0 MNMOS1 W=3U L=3U

M3 3 3 1 0 MNMOS1 W=3U L=3U

iI

= 50uA

M4 4 3 2 0 MNMOS1 W=3U L=3U

M3

M4

IIN 0 3

40uA

VOUT 4 0

iI

= 40uA

.DC VOUT 0 5 0.1

+ IIN 10U 60U 10U

iOUT

.PRINT DC ID(M4)

iI

= 30uA

.PROBE

.END

20uA

iI

= 20uA

M1

M2

iI

= 10uA

VSS

0

0

1

2

3

4

5

vOUT

Example of Small Signal Output Resistance Calculation -

ii

io

+

+

+

v3

rds3

gm3v3

v4

rds4

gm4(v3+v1-v2)

-

gmbs v2

-

v1=v3

=0

io

vo

+

+

v1

rds1

gm1v1

v2

rds2

gm2v1

-

-

-

1). vo = v4 + v2 = rds4 [io - gm4(v3 + v1 - v2) + gmbs4v2] + rds2(io -gm2v1) 2). v2 = iords2

3). vo = io [rds4 + (gm4rds2)rds4 + (rds2gmbs4)rds4 + rds2]

vo

4). rout = io = rds4 + rds2 + rds2rds4(gm4 + gmbs4)

Allen and Holberg - CMOS Analog Circuit Design

Wilson Current Mirror

Circuit and Performance-

iI	iO	65.5uA
M3
		45.0uA
M1	M2	iO
VSS		22.5uA
		0
		0	1

Wilson Current Source

M1 1 2 0 0 MNMOS W=15U L=3U

M2 2 2 0 0 MNMOS W=15U L=3U

M3 3 1 2 0 MNMOS W=15U L=3U R 1 0 100MEG

.MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, GAMMA=0.8 PHI=0.6

IIN 0 1 VOUT 3 0

.DC VOUT 0 5 0.1 IIN 10U 80U 10U

.PRINT DC V(2) V(1) ID(M3)

.PROBE

.END

Page V.4-9

Iin = 80uA

70uA

60uA

50uA

40uA

30uA

20uA

10uA

2

3

4

5

vOUT

Principle of Operation:

Series negative feedback increase output resistance

1. Assume input current is constant and that there is high resistance to ground from the gate of M3 or drain of M1.

2.A positive increase in output current causes an increase in vGS2.

3.The increase in vGS2 causes an increase in vGS1.

4.The increase in vGS1 causes an increase in iD1.

5.If the input current is constant, then the current through the resistance to

ground from the gate of M3 or the drain of M1 decreases resulting in a decrease in vGS3.

6. A decrease in vGS3 causes a decrease in the output current opposing the assumed increase in step 2.