Allen and Holberg - CMOS Analog Circuit Design

	Allen and Holberg - CMOS Analog Circuit Design			Page IV.3-3
	f2	=	ε s i	(7)
			[vGS - VT - (UTRA)vDS]Co x

The units of f1 and f2 are FV2/cm2 and cm/V respectively. Notice that f2

includes the parameter UTRA, which is an unknown. UTRA is disabled in most SPICE models.

Equation (5) can be manipulated algebraically to yield

	i	D		= log(µo) + UEXP[log(UCRIT)] + UEXP[log(f2)]
log
	f1

This is in the familiar form of Eq. (4) with

x= log(f2)

=iD

ylog f1

m = UEXP

b = log(µo) + UEXP[log(UCRIT)]

(8)

(9)

(10)

(11)

(12)

By plotting Eq. (8) and measuring the slope, UEXP can be determined. The y-intercept can be extracted from the plot and UCRIT can be determined by back calculation given UEXP, µo, and the intercept, b.

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Allen and Holberg - CMOS Analog Circuit Design

Page IV.4-1

III.Characterization of Substrate Bipolar

Parameters of interest are: β dc, and JS.

For vBE >> kT/q,

vBE = kT		i	C
		ln			(1)
	q	JSAE
and
βdc =	iE	− 1			(2)
	iB

AE is the cross-sectional area of the emitter-base junction of the BJT.

iE = iB(β dc + 1)

(3)

Plot iB as a function of iE and measure the slope to determine β dc.

Once β dc is known, then Eq. (1) can be rearranged and modified as follows.

vBE =	k T		iEβ d c		−	k T	ln(JSAE) =	k T	ln(α dciE) −	k T
	q	ln				q		q		q
		1 + β d c

ln(JSAE)

Plotting ln[iEβ dc/(1 + β dc)] versus vBE results in a graph where m = slope = kTq

and

k T
b = y-intercept = − q	ln(JSAE)

Since the emitter area is known, JS can be determined directly.

(5)

(6)

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Allen and Holberg - CMOS Analog Circuit Design

Page IV.5-1

IV. Characterization of Resistive Components

•Resistors

•Contact resistance

Characterize the resistor geometry exactly as it will be implemented in a design. Because

•sheet resistance is not constant across the width of a resistor

•the effects of bends result in inaccuracies

•termination effects are not accurately predictable

Figure B.5-1 illustrates a structure that can be used to determine sheet resistance, and geometry width variation (bias).

Force a current into node A with node F grounded while measuring the voltage drops across BC (Vn) and DE (Vw), the resistors Rn and Rw can

be determined as follows

Rn = VIn

Rw = VIw

The sheet resistance can be determined from these to be

W n - Bias
RS = Rn	Ln

W w - Bias
RS = Rw	Lw

where

Rn = resistance of narrow resistor (Ω)

Rw = resistance of wide resistor (Ω)

RS = sheet resistance of material (polysilicon, Ω/square)

Ln = drawn length of narrow resistor

(1)

(2)

(3)

(3)

diffusion etc.

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Allen and Holberg - CMOS Analog Circuit Design Page IV.5-2

Lw = drawn length of wide resistor

Wn = drawn width of narrow resistor

Ww = drawn width of wide resistor

Bias = difference between drawn width and actual device width

Rw

A

Rn

F

Wn

Ww

Ln

Lw

B

C

D

E

Figure B.5-1 Sheet resistance and bias monitor.

Solving equations (3) and (4) yields

Bias =

W n

- k Ww

(5)

1

- k

where
k =	RwLn						(6)
	RnLw
and
RS	W n - Bias			W w - Bias			(7)
	= Rn	Ln		= Rw	Lw

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Allen and Holberg - CMOS Analog Circuit Design

Page IV.5-3

Determining sheet resistance and contact resistance

10 squares

RA=220 Ω

20 squares

RB=420 Ω

Figure B.5-2 Two resistors used to determine RS and RC.

RA = R1 + 2Rc;	R1 = N1RS
and
RB = R2 + 2Rc;	R2 = N2RS

N1 is the number of squares for R1 RS is the sheet resistivity in Ω/square Rc is the contact resistance.

= R B - R A R S N 2 - N 1

and

2Rc = RA − N1RS = RB − N2RS

(8)

(9)

(10)

(11)

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Allen and Holberg - CMOS Analog Circuit Design

Page IV.5-4

Voltage coefficient of lightly-doped resistors

R =

V1 − V2

VBIAS =

V1 + V2

I R

2

V1

IR

V

2

VSS

Figure B.5-3 N-well resistor illustrating back-bias dependence.

	27.0
	26.5
(kΩ)	26.0
Resistance
	25.5
	25.0
	1.0	2.0	3.0	4.0	5.0	6.0	7.0	8.0
				Back bias (volts)

Figure B.5-4 N-well resistance as a function of back-bias voltage

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Allen and Holberg - CMOS Analog Circuit Design

Page IV.5-5

Contact Resistance

	Pad 1
Metal pads	Diffusion or
	polysilicon
Pad 3	Pad 4
	Metal pads
	Pad 2
	Pad 1
	RC

R

RC

Pad 4

R

RC

Pad 3

RM

RM

Pad 2

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Allen and Holberg - CMOS Analog Circuit Design

Page IV.5-1

V.Characterization of Capacitance

MOS capacitors

CGS, CGD, and CGB

Depletion capacitors

CDB and CSB

Interconnect capacitances

Cpoly-field, Cmetal-field, and Cmetal-poly (and perhaps multi-metal capacitors

SPICE capacitor models

CGS0, CGD0, and CGB0 (at VGS = VGB = 0).

Normally SPICE calculates CDB and CSB using the areas of the drain and source and the junction (depletion) capacitance, CJ (zero-bias value), that it

calculates internally from other model parameters. Two of these model parameters, MJ and MJSW, are used to calculate the depletion capacitance as a function of voltage across the capacitor.

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Allen and Holberg - CMOS Analog Circuit Design	Page IV.5-2
CGS0, CGD0, and CGB0

CGS0 and CGD0, are modeled in SPICE as a function of the device width, while the capacitor CGB0 is per length of the device

Measure the CGS of a very wide transistor and divide the result by the width in order to get CGS0 (per unit width).

Source

Drain

Source

Gate

Figure B.6-1 Structure for determining CGS and CGD.

Cmeas = W(n)(CGS0 + CGD0)

(1)

where

Cmeas = total measured capacitance

W = total width of one of the transistors n = total number of transistors

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Allen and Holberg - CMOS Analog Circuit Design

Page IV.5-3

For very narrow transistors, the capacitance determined using the previous technique will not be very accurate because of fringe field and other edge effects at the edge of the transistor. In order to characterize CGS0 and

CGD0 for these narrow devices, a structure similar to that given in Fig.

B.6-1 can be used, substituting different device sizes. Such a structure is given in Fig. B.6-3. The equations used to calculate the parasitic capacitances are the same as those given in Eq. (1).

	Metal drain		Metal source	Polysilicon
	interconnect		interconnect
					gate
Drain	Source	Drain	Source

Figure B.6-3 Structure for measuring CGS and CGD, including fringing effects, for transistors having small L.

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