Allen and Holberg - CMOS Analog Circuit Design

Allen and Holberg - CMOS Analog Circuit Design Page III.1-6

SIMPLIFIED SAH MODEL DERIVATION

Model-

+
vGS	-			+
			iD	-vDS
n+			n+
v(y)		dy	Drain
Source				y
p-		y y+dy	L
0

Derivation-

•

Let the charge per unit area in the channel inversion layer be

Q (y) = C

ox

[v

GS

− v(y) − V

T

]

(coulombs/cm2)

I

•

Define sheet conductivity of the inversion layer per square as

σ

= µoQ (y)

cm2

coulombs

=

amps

=

1

S

volt

Ω/sq.

I

v·s

cm2

• Ohm's Law for current in a sheet is

	JS =	iD	=	σ E	= σS	dv	.
		W				dy
				S y
	Rewriting Ohm's Law gives,
		iD			iDdy
	dv = σSW			dy = µoQ (y)W
					I

where dv is the voltage drop along the channel in the direction of y.

Rewriting as

iD dy = WµoQI(y)dv

and integrating along the channel for 0 to L gives

L	vDS	vDS
⌠	⌠	⌠
⌡iDdy =	⌡WµoQI(y)dv =	⌡WµoCox[vGS−v(y)−VT] dv
0	0	0

After integrating and evaluating the limits

Wµ C

i = o ox (v −V )v −

D L GS T DS

v2 DS

2

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-7

ILLUSTRATION OF THE SAH EQUATION

Plotting the Sah equation as iD vs. vDS results in -

iD

vDS = vGS - VT

Non-Sat Region

Saturation Region

Increasing values of vGS

vDS

Define vDS(sat) = vGS − VT

Regions of Operation of the MOS Transistor

1.) Cutoff Region:

iD = 0, vGS − VT < 0 (Ignores subthreshold currents)

2.) Non-saturation Region

i

=

µCoxW

, 0 < v

< v

− V

D

2L

2(vGS − VT) − vDS v

DS

DS

T

GS

3.) Saturation Region

i

=

µCoxW

2

, 0 < v

− V

< v

D

2L

(vGS − VT)

GS

T

DS

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-8

SAH MODEL ADJUSTMENT TO INCLUDE EFFECTS OF VDS ON VT

From the previous derivation:

L	vDS	vDS
⌠	⌠	⌠
⌡ iD dy =	⌡ WµoQI(y)dy =	⌡ WµoCox[vGS − v(y) − VT]dv
0	0	0

Assume that the threshld voltage varies across the channel in the following way:

VT(y) = VT + v(y)

where VT is the value of the threshold voltage at the source end of the channel.

Integrating the above gives,

iD =	WµoCox		)	v2(y) vDS
	L	(vGS−VT)v(y) − (1+		2
					0
or
	WµoCox			v2DS
iD = L			)	2
		(vGS−VT)vDS − (1+

To find vDS(sat), set the derivative of iD with respect to vDS equal to zero and solve for vDS = vDS(sat) to get,

vGS − VT vDS(sat) = 1 +

Therefore, in the saturation region, the drain current is

WµoCox		2
iD = 2(1+ )L vGS − VT

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-9

EFFECTS OF BACK GATE (BULK-SOURCE)

Bulk-Source (vBS) influence on the transconductance characteristics-

iD	Decreasing values
	of bulk-source voltage
	VBS = 0
	vDS ≥ vGS - VT

vGS

VT0 VT1	VT2 V
	T3

In general, the simple model incorporates the bulk effect into VT by the following empirically developed equation-

VT(VBS) =VT0 + γ 2|φf| + |vBS| − γ 2|φf|

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-10

EFFECTS OF THE BACK GATE - CONTINUED

Illustration-

VSB0 = 0V:

	VSB0=0V		Gate	Drain
	-	+	VGS>VT	VDS>0
Bulk		Source	Poly
	p+	n+		n+
p-	Substrate/Bulk

VSB1>0V:

VSB1

- +

Bulk Source

p+

n+

p- Substrate/Bulk

VSB2 > VSB1:

VSB2

- +

Bulk Source

p+

n+

p- Substrate/Bulk

Gate Drain

VGS>VT VDS>0

Poly

n+

Gate Drain

VGS>VT VDS>0

Poly

n+

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-11

SAH MODEL INCLUDING CHANNEL LENGTH MODULATION

N-channel reference convention:

D iD +

G+ + B vDS

vGS vBS

- - -

S

Non-saturation-

iD =	WµoCox		vDS2
	L	(vGS − VT)vDS −
			2

Saturation-
iD =	WµoCox		vDS(sat)2	(1 + λvDS)
	L	(vGS − VT)vDS(sat) −
			2
= WµoCox		(vGS − VT) 2 (1 + λvDS)
	2L

where:

µo = zero field mobility (cm2/volt·sec)

Cox = gate oxide capacitance per unit area (F/cm2)

λ= channel-length modulation parameter (volts-1) VT = VT0 + γ 2|φf| + |vBS| − 2|φf|

VT0 = zero bias threshold voltage

γ = bulk threshold parameter (volts1/2)

2|φf| = strong inversion surface potential (volts)

When solving for p-channel devices, negate all voltages and use the n- channel model with p-channel parameters and negate the current. Also negate VT0 of the p device.

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-12

OUTPUT CHARACTERISTICS OF THE MOS TRANSISTOR

iD /ID0

vDS = vGS - VT

vGS -VT

1.0

= 1.0

VGS0 - VT

Non-Sat

Saturation Region

Region

vGS-VT

0.75

= 0.867

VGS0 - VT

Channel modulation effects

vGS-VT

= 0.707

0.5

V

- V

GS0

T

vGS-VT

= 0.5

V

- V

0.25

GS0

T

vGS-VT

Cutoff Region

= 0

VGS0 - VT

0

vDS

0

0.5

1.0

1.5

2.0

2.5

VGS0 - VT

Notation:

W	W
ß = K' L = ( oCox)	L

Note:

oCox = K'

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-13

GRAPHICAL INTERPRETATION OF λ

Assume the MOS is transistor is saturated-

i		=	µCoxW
	D		2L		(vGS − VT) 2(1 + λvDS)
Define iD(0) = iD when vDS = 0V.
i	D	(0) =		µCoxW		(vGS − VT)2
					2L

Now,

iD = iD(0) [1+λvDS] = iD(0) + λiD(0) vDS

or

vDS = λiD (0) iD	− λ
1	1
Matching with y = mx + b gives
			vDS
							1
	1						λiD(0)
						iD(0)	iD
	-1
			λ
or						iD
		iD3(0)					VGS3
		iD2(0)					VGS2
		i	D1		(0)

VGS1

vDS

-1

λ

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-14

SPICE LEVEL 1 MODEL PARAMETERS FOR A TYPICAL

BULK CMOS PROCESS (0.8 m)

	Model	Parameter	Typical Parameter
			Value		Units
	Parameter	Description
			NMOS	PMOS
	VT0	ThresholdVoltage forVBS = 0V	0.75±0.15	−0.85±0.15	Volts
	K'	Transconductance Parameter	110±10%	50±10%	µA/V2
		(sat.)
	γ	Bulk Threshold Parameter	0.4	0.57	V
	λ	Channel Length Modulation	0.04 (L=1 m)	0.05 (L = 1 m)	V-1
			0.01 (L=2 m)	0.01 (L = 2 m)
		Parameter
	φ = 2φF	Surface potential at strong	0.7	0.8	Volts
		inversion

These values are based on a 0.8 m silicon-gate bulk CMOS n-well process.

Allen and Holberg - CMOS Analog Circuit Design

Page III.1-15

WEAK INVERSION MODEL (Simple)

				iD (nA)
							Weak
iD				1000.0			inversion
							region		Strong
				100.0					inversion
				10.0					region
				1.0
0		VT VON	vGS	0			VT VON		vGS

This model is appropriate for hand calculations but it does not accommodate a smooth transition into the strong-inversion region.

i			W	I		qvGS
	D		L		DO	exp
						nkT

The transition point where this relationship is valid occurs at approximately

kT vgs < VT + n q

Weak-Moderate-Strong Inversion Approximation

			Moderate
			inversion region
iD (nA)
		Weak
1000.0		inversion	Strong
		region
100.0			inversion
			region
10.0
1.0

0

vGS