Allen and Holberg - CMOS Analog Circuit Design

Allen and Holberg - CMOS Analog Circuit Design

Page V.1-17

POSSIBLE SOLUTIONS TO CLOCK FEEDTHROUGH

1.) Dummy transistor (MD) -

φ	φ
W1	W	W
L1	D =	1
	L	2L
	D	1
M1	MD
VSS	V
	SS

Complete cancellation is difficult.

Requires a complementary clock.

2.) Limit the clock swing when one terminal of the switch is at a defined potential.

	vG
	0V
	C
+	+
vin > 0	vout
-	VSS
	-

vG

3VT

2VT

VT

t

ON

OFF

ON

Allen and Holberg - CMOS Analog Circuit Design

Page V.1-18

CMOS SWITCHES

"Transmission Gate"

φ

VSS

A B

VDD

φ

Advantages -

1.) Larger dynamic range.

2.) Lower ON resistance. Disadvantages -

1.) Requires complementary clock.

2.) Requires more area.

Allen and Holberg - CMOS Analog Circuit Design

Page V.1-19

DYNAMIC RANGE LIMITATIONS OF SWITCHES

Must have sufficient vGS to give a sufficiently low on resistance

Example:

VDD

Switch On Resistance

50µ

2µ

A

+

VDD

VAB

50µ

-

2µ

3kΩ

2.5kΩ

V

= 4V

DD

2kΩ

V

= 4.5V

DD

1.5kΩ

V

= 5V

DD

1kΩ

0.5kΩ

0kΩ

0V

1V

2V

VAB

B

1 A

3V

4V

5V

SPICE File:

Simulation of the resistance of a CMOS transmission switch M1 1 3 2 0 MNMOS L=2U W=50U

M2 1 0 2 3 MPMOS L=2U W=50U

.MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5

.MODEL MPMOS PMOS VTO=-0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5 VDD 3 0

VAB 1 0

IA 2 0 DC 1U

.DC VAB 0 5 0.02 VDD 4 5 0.5

.PRINT DC V(1,2)

.END

Allen and Holberg - CMOS Analog Circuit Design

Page V.1-20

“Brooklyn Bridge” Effect

If N-channel and P-channel devices are “resistively” scaled (i.e., sized to have the same conductance at equivalent terminal conditions) the resistance versus voltage (common mode) will appear as shown below.

	Nch on	Nch on; Pch on			Pch on
	Pch off				Nch off
280
270					5v
260
R 250					I d
					5v
240
230					V
220					0.1
210
0	1	2	3	4	5

V

Allen and Holberg - CMOS Analog Circuit Design

Page V.1-21

VOLTAGE DOUBLER USE TO PROVIDE GATE OVERDRIVE

Example

VDD

M1				φA
φA	CPump
				M6
		M4		+
			M7	M8
		φA
M2	φB			VDBL
				CHold
	M3
		φB	φA	φB
		M5		-

VSS

φA

φB

Operation:

1.φA low, φB high - CPump is charged to VDD-VSS.

2.φA high, φB low - CPump transfers negative charge to CHold

V	DBL	≈ -0.5 V	DD	- V
					S S

3.Eventually, VDBL approaches the voltage of -VDD + VSS. If VDD = - VSS, then VDBL ≈ - 2VDD.

Allen and Holberg - CMOS Analog Circuit Design

Page V.1-22

SUMMARY OF MOS SWITCHES

•Symmetrical switching characteristics

•High OFF resistance

•Moderate ON resistance (OK for most applications)

•Clock feedthrough is proportional to size of switch (W) and inversely proportional to switching capacitors.

•Complementary switches help increase dynamic range.

•As power supply reduces, switches become more difficult to fully turn on.

•Switches contribute a kT/C noise which folds back into the baseband.

Allen and Holberg - CMOS Analog Circuit Design

Page V.2-1

V.2 - DIODES AND ACTIVE RESISTORS

MOS ACTIVE RESISTORS

Realizations

+

v

i -

I-V Characteristics -

i

AC

DC

v

Small signal

		i
G
+
v	gm v	gmbs vbs	rds
S -

		+		When the drain is connected to the
	i		gate, the transistor is always saturated.
		v		vDS ≥ vGS - VT
				vD - vS ≥ vG - vS - VT
		- vDG ≥ -VT where VT > 0
				Large Signal

i

=

i

D

=

( K'W ) [ v

GS

- V

T

]2

β

2L

=

( v

GS

- V

T

) 2 ,

ignore

λ

2

or

v = vDS = vGS = VT +

2iD

β

D

S

If VBS = 0 ,	then ROUT =	v	=	1	≈	1
If VBS ≠ 0?		i		gM + gD S		gM
Note:	Generally, gm ≈ 10 gmbs ≈ 100 gds

Allen and Holberg - CMOS Analog Circuit Design

Page V.2-2

VOLTAGE DIVISION USING ACTIVE RESISTORS

Objective : Derive a voltage Vout from VSS and VDD

VDD

M2

Vout

M1

VSS

Equating

iD1 to iD2 results in :

v

=

β 2

v

- V

+ V

DS1

β1

DS2

T 2

T1

where

vGS1 = vDS1

and

vGS2 = vDS2

Example :

If

VDD = -VSS = 5 volts,

Vout = 1 volt, and ID1 = ID2 = 50 µamps,

then use the model parameters of Table 3.1-2 to find W/L ratios.

i

D1

=

β

( v

GS

- V

T

) 2

2

β1

=

4.0 µA/V2

β2

=

11.1 µA/V2

K'n =

17

µA/V2

K'p =

8 µA/V2

then ( W/L )1

=

1

and

( W/L )2

=

1.34

4.25

Allen and Holberg - CMOS Analog Circuit Design

Page V.2-3

EXTENDED DYNAMIC RANGE OF ACTIVE RESISTORS

Concept:

		I		I
-		+
	I1
VC		I2
+	M1	vDS M2	+	R
			VC
		-	-

Consider :

Assume both devices are non-saturated

2

v DS

I1 = β1 (vDS + VC - VT)vDS -

2

2

v DS

I2 = β2 (VC - VT )vDS -

2

2

2

I = I

+ I

= β

v

2

+ (V

- V

)v

v DS

+ (V

- V

)v

-

v DS

1

2

D S

C

T

D S

-

2

C

T

D S

2

I = 2β(VC - VT)vDS

R =

1

2β(VC - VT)

Allen and Holberg - CMOS Analog Circuit Design

Page V.2-4

Implementation :

	VDD
	+
M3A	-	VC

S	+		M1
	VGS	S	D
	G -
M2A		i	M2
		-	i
			vDS +
		R
			VSS

M3B

+

VGS	S
-
G	M2B