- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Resources
- •Code Examples
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •Erase
- •Write
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Overview
- •Three-wire Mode
- •Two-wire Mode
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Features
- •Overview
- •Physical Interface
- •Limitations of debugWIRE
- •debugWire Data Register – DWDR
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •Maximum Speed vs. VCC
- •Idle Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev C
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06
- •Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05
- •Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04
- •Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04
- •Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04
- •Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04
- •Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03
- •Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03
- •Table of Contents
Pin
Configurations
Figure 1. Pinout ATtiny2313
PDIP/SOIC
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VCC |
(RESET/dW) PA2 |
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20 |
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(RXD) PD0 |
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2 |
19 |
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PB7 (UCSK/SCL/PCINT7) |
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(TXD) PD1 |
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3 |
18 |
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PB6 (MISO/DO/PCINT6) |
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(XTAL2) PA1 |
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4 |
17 |
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PB5 (MOSI/DI/SDA/PCINT5) |
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(XTAL1) PA0 |
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5 |
16 |
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PB4 (OC1B/PCINT4) |
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(CKOUT/XCK/INT0) PD2 |
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6 |
15 |
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PB3 (OC1A/PCINT3) |
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(INT1) PD3 |
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7 |
14 |
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PB2 (OC0A/PCINT2) |
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(T0) PD4 |
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8 |
13 |
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PB1 (AIN1/PCINT1) |
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(OC0B/T1) PD5 |
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9 |
12 |
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PB0 (AIN0/PCINT0) |
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GND |
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10 |
11 |
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PD6 (ICP) |
MLF
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PA2 (RESET/dW) |
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PB7 (UCSK/SCK/PCINT7) |
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PB6 (MISO/DO/PCINT6) |
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PD0 (RXD) |
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VCC |
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(TXD) PD1 |
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20 |
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19 |
18 |
17 |
16 |
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1 |
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15 |
PB5 (MOSI/DI/SDA/PCINT5) |
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XTAL2) PA1 |
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2 |
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14 |
PB4 (OC1B/PCINT4) |
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(XTAL1) PA0 |
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3 |
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13 |
PB3 (OC1A/PCINT3) |
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(CKOUT/XCK/INT0) PD2 |
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4 |
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12 |
PB2 (OC0A/PCINT2) |
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(INT1) PD3 |
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5 |
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11 |
PB1 (AIN1/PCINT1) |
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6 |
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7 |
8 |
9 |
10 |
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(T0) PD4 |
(OC0B/T1) PD5 |
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GND |
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(ICP) PD6 |
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(AIN0/PCINT0) PB0 |
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NOTE: Bottom pad should be soldered to ground.
Overview
The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2 ATtiny2313
2543L–AVR–08/10
ATtiny2313
Block Diagram
Figure 2. |
Block Diagram |
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XTAL1 |
XTAL2 |
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PA0 - PA2 |
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PORTA DRIVERS |
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VCC |
DATA REGISTER |
DATA DIR. |
INTERNAL |
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PORTA |
REG. PORTA |
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CALIBRATED |
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OSCILLATOR |
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8-BIT DATA BUS |
INTERNAL |
OSCILLATOR |
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OSCILLATOR |
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GND |
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PROGRAM |
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STACK |
WATCHDOG |
TIMING AND |
RESET |
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COUNTER |
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POINTER |
TIMER |
CONTROL |
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MCU CONTROL |
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PROGRAM |
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SRAM |
REGISTER |
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FLASH |
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MCU STATUS |
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ON-CHIP |
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DEBUGGER |
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REGISTER |
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INSTRUCTION |
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GENERAL |
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REGISTER |
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PURPOSE |
TIMER/ |
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REGISTER |
COUNTERS |
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INSTRUCTION |
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INTERRUPT |
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DECODER |
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UNIT |
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EEPROM |
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CONTROL |
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ALU |
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LINES |
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USI |
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STATUS |
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REGISTER |
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PROGRAMMING |
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SPI |
USART |
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LOGIC |
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ANALOG COMPARATOR |
DATA REGISTER |
DATA DIR. |
DATA REGISTER |
DATA DIR. |
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PORTB |
REG. PORTB |
PORTD |
REG. PORTD |
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PORTB DRIVERS |
PORTD DRIVERS |
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PB0 - PB7 |
PD0 - PD6 |
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3
2543L–AVR–08/10
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
4 ATtiny2313
2543L–AVR–08/10