- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Resources
- •Code Examples
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •Erase
- •Write
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Overview
- •Three-wire Mode
- •Two-wire Mode
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Features
- •Overview
- •Physical Interface
- •Limitations of debugWIRE
- •debugWire Data Register – DWDR
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •Maximum Speed vs. VCC
- •Idle Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev C
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06
- •Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05
- •Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04
- •Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04
- •Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04
- •Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04
- •Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03
- •Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03
- •Table of Contents
|
|
|
|
|
|
|
|
ATtiny2313 |
|
|
|
|
|
|
|
|
|
||
|
Fuse Bits |
|
|
|
|
|
|
||
|
The ATtiny2313 has three Fuse bytes. Table 67 and Table 68 describe briefly the functionality of |
||||||||
|
|||||||||
|
|
all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logi- |
|||||||
|
|
cal zero, “0”, if they are programmed. |
|
|
|
|
|||
|
|
Table 66. Fuse Extended Byte |
|
|
|
|
|||
|
|
Fuse Extended |
Bit |
|
|
|
|
|
|
|
|
Byte |
No |
|
Description |
Default Value |
|
||
|
|
|
7 |
|
– |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
6 |
|
– |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
5 |
|
– |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4 |
|
– |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3 |
|
– |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
|
– |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
|
– |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SELFPRGEN |
0 |
|
Self Programming Enable |
1 |
(unprogrammed) |
|
|
|
|
|
|
|
|
|
|||
|
|
Notes: 1. Enables SPM instruction. See “Self-Programming the Flash” on page 153. |
|||||||
|
|
Table 67. Fuse High Byte |
|
|
|
|
|
||
|
|
|
Bit |
|
|
|
|
|
|
|
|
Fuse High Byte |
No |
|
Description |
Default Value |
|
||
|
|
DWEN(3) |
7 |
|
debugWIRE Enable |
1 |
(unprogrammed) |
|
|
|
|
EESAVE |
6 |
|
EEPROM memory is preserved |
1 |
(unprogrammed, EEPROM |
|
|
|
|
|
through the Chip Erase |
not preserved) |
|
||||
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
SPIEN(1) |
5 |
|
Enable Serial Program and Data |
0 |
(programmed, SPI prog. |
|
|
|
|
|
Downloading |
enabled) |
|
||||
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
WDTON(2) |
4 |
|
Watchdog Timer always on |
1 |
(unprogrammed) |
|
|
|
|
BODLEVEL2(4) |
3 |
|
Brown-out Detector trigger level |
1 (unprogrammed) |
|
||
|
|
BODLEVEL1(4) |
2 |
|
Brown-out Detector trigger level |
1 (unprogrammed) |
|
||
|
|
BODLEVEL0(4) |
1 |
|
Brown-out Detector trigger level |
1 (unprogrammed) |
|
||
|
|
RSTDISBL(5) |
0 |
|
External Reset disable |
1 (unprogrammed) |
|
Note: 1. The SPIEN Fuse is not accessible in serial programming mode.
2.See “Watchdog Timer Control Register - WDTCSR” on page 42 for details.
3.Never ship a product with the DWEN Fuse programmed regardless of the setting of Lock bits. A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This may increase the power consumption.
4.See Table 16 on page 35 for BODLEVEL Fuse decoding.
5.See “Alternate Functions of Port A” on page 53 for description of RSTDISBL Fuse.
159
2543L–AVR–08/10