- •Features
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Resources
- •Code Examples
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •Erase
- •Write
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •Clock Sources
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •Parity Generator
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Using MPCM
- •Overview
- •Three-wire Mode
- •Two-wire Mode
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Features
- •Overview
- •Physical Interface
- •Limitations of debugWIRE
- •debugWire Data Register – DWDR
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •Maximum Speed vs. VCC
- •Idle Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev C
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06
- •Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05
- •Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04
- •Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04
- •Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04
- •Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04
- •Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03
- •Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03
- •Table of Contents
ATtiny2313
Table of Contents
Features 1
Pin Configurations 2
General Information 6
Resources 6
Code Examples 6
Disclaimer 6
AVR CPU Core 7
Introduction 7
Architectural Overview 7
ALU – Arithmetic Logic Unit 8
Status Register 8
General Purpose Register File 9
Instruction Execution Timing 11
Reset and Interrupt Handling 12
AVR ATtiny2313 Memories 14
In-System Reprogrammable Flash Program Memory 14
EEPROM Data Memory 16
I/O Memory 20
System Clock and Clock Options 22
Clock Systems and their Distribution 22
Clock Sources 23
Default Clock Source 23
Crystal Oscillator 23
Calibrated Internal RC Oscillator 25
System Clock Prescalar 28
Power Management and Sleep Modes 30
Idle Mode 30
Power-down Mode 31
Standby Mode 31
Minimizing Power Consumption 31
System Control and Reset 33
Interrupts 44
Interrupt Vectors in ATtiny2313 44
I/O-Ports 46
Introduction 46
i
2543L–AVR–08/10
Ports as General Digital I/O 47
Alternate Port Functions 51
External Interrupts 59
Pin Change Interrupt Timing 59
8-bit Timer/Counter0 with PWM 62
Overview 62
Timer/Counter Clock Sources 63 Counter Unit 63
Output Compare Unit 64 Compare Match Output Unit 65 Modes of Operation 66
Timer/Counter Timing Diagrams 71
Timer/Counter0 and Timer/Counter1 Prescalers 80
16-bit Timer/Counter1 82
Overview 82
Accessing 16-bit Registers 84
Counter Unit 88
Input Capture Unit 89
Output Compare Units 90
Modes of Operation 94
USART 111
Overview 111
Clock Generation 112
Frame Formats 115
USART Initialization 116
Asynchronous Data Reception 124
Universal Serial Interface – USI 138
Overview 138
Functional Descriptions 139
Alternative USI Usage 144
USI Register Descriptions 144
Analog Comparator 149
debugWIRE On-chip Debug System 151
Features 151
Overview 151 Physical Interface 151
Software Break Points 152 Limitations of debugWIRE 152
ii ATtiny2313
2543L–AVR–08/10
ATtiny2313
debugWIRE Related Register in I/O Memory 152
Self-Programming the Flash 153
Memory Programming 158
Program And Data Memory Lock Bits 158
Signature Bytes 160
Calibration Byte 160
Page Size 160
Parallel Programming Parameters, Pin Mapping, and Commands 161
Serial Programming Pin Mapping 163
Parallel Programming 163
Serial Downloading 172
External Clock Drive 179
ATtiny2313 Typical Characteristics 181
Errata 219
ATtiny2313 Rev C 219
ATtiny2313 Rev B 219
ATtiny2313 Rev A 219
Datasheet Revision History 220
Rev. 2543L - 8/10 220
Rev. 2543K - 03/10 220
Rev. 2543J - 11/09 220
Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06 220
Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05 220
Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04 221
Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04 221
Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04 221
Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04 221
Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03 222
Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03 222
iii
2543L–AVR–08/10
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2543L–AVR–08/10