03.Combinational circuits
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Chapter 3 − Combinational Circuits
COMPONENT myand2 PORT( i1, i2: IN BIT;
o: OUT BIT); END COMPONENT;
COMPONENT myand3 PORT( i1, i2, i3: IN BIT; o: OUT BIT);
END COMPONENT; COMPONENT myor2 PORT(
i1, i2: IN BIT; o: OUT BIT);
END COMPONENT; COMPONENT myor3 PORT(
i1, i2, i3: IN BIT; o: OUT BIT);
END COMPONENT; COMPONENT myor4 PORT(
i1, i2, i3, i4: IN BIT; o: OUT BIT);
END COMPONENT; COMPONENT myxnor2 PORT(
i1, i2: IN BIT; o: OUT BIT);
END COMPONENT; COMPONENT myxor2 PORT(
i1, i2: IN BIT; o: OUT BIT);
END COMPONENT;
SIGNAL j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z: BIT; BEGIN
U1: INV port map(i2,j); U2: INV port map(i1,k); U3: INV port map(i0,l);
U4: myXNOR2 port map(i2, i0, z); U5: myOR3 port map(i3, i1, z, a); U6: myXNOR2 port map(i1, i0, y); U7: myOR2 port map(j, y, b);
U8: myOR3 port map(i2, k, i0, c); U9: myAND2 port map(i1, l, x); U10: myAND2 port map(j, l, w); U11: myAND2 port map(j, i1, v);
U12: myAND3 port map(i2, k, i0, t); U13: myOR4 port map(x, w, v, t, d); U14: myAND2 port map(i1, l, s); U15: myAND2 port map(j, l, r);
U16: myOR2 port map(s, r, e); U17: myAND2 port map(i2, k, q); U18: myAND2 port map(i2, l, p); U19: myAND2 port map(k, l, o);
U20: myOR4 port map(i3, q, p, o, f); U21: myXOR2 port map(i2, i1, n); U22: myAND2 port map(i1, l, m);
U23: myOR3 port map(i3, n, m, g); END Structural;
Figure 8. Structural VHDL description of the BCD to 7-segment decoder.
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Chapter 3 − Combinational Circuits |
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3.7.2 Dataflow BCD to 7-Segment Decoder
The dataflow VHDL description of the BCD to 7-segment decoder is shown in Figure 9. In the architecture section, seven concurrent signal assignment statements are used; one for each of the seven Boolean functions, which corresponds to the seven segments. For example, the equation for segment a was given as
a = I3 + I1 + (I2 I0)
This is converted to the signal assignment statement
Segs(1) <= I(3) OR I(1) OR NOT (I(2) XOR I(0));
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bcd IS PORT (
I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Segs: OUT std_logic_vector (1 TO 7));
END bcd; |
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ARCHITECTURE Dataflow OF bcd IS |
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BEGIN |
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Segs(1) <= I(3) OR I(1) OR NOT (I(2) XOR I(0)); |
-- seg a |
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Segs(2) <= (NOT I(2)) OR |
NOT (I(1) XOR |
I(0)); |
-- seg b |
Segs(3) <= I(2) OR (NOT I(1)) OR I(0); |
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-- seg c |
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Segs(4) <= (I(1) AND NOT |
I(0)) OR (NOT |
I(2) AND NOT I(0)) |
-- seg d |
OR (NOT I(2) AND I(1)) OR (I(2) AND NOT I(1) AND I(0)); |
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Segs(5) <= (I(1) AND NOT |
I(0)) OR (NOT |
I(2) AND NOT I(0)); |
-- seg e |
Segs(6) <= I(3) OR (I(2) |
AND NOT I(1)) |
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-- seg f |
OR (I(2) AND NOT I(0)) OR (NOT I(1) AND NOT I(0)); |
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Segs(7) <= I(3) OR (I(2) |
XOR I(1)) OR (I(1) AND NOT I(0)); |
-- seg g |
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END Dataflow; |
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Figure 9. Dataflow VHDL description of the BCD to 7-segment decoder.
3.7.3 Behavioral BCD to 7-Segment Decoder
The behavioral VHDL description of the BCD to 7-segment decoder. is shown in Figure 10. In the architecture section, a process block is used. All the statements inside the process block are executed sequentially. The process block itself, however, is treated as a single concurrent statement. Thus, the architecture section can have two or more process blocks together with other concurrent statements, and these will all execute concurrently.
The parenthesized list of signals after the PROCESS keyword is referred to as the sensitivity list The purpose of the sensitivity list is that when a value for any of the listed signals changes, the entire process block is executed from the beginning to the end.
In the example, there is only one CASE statement inside the process block. Depending on the value of I, one of the WHEN part will be executed. A string of seven bits, which matches the on-off values of the seven segments as discussed in Figure 6, will be assigned to the output signal Segs. If the value of I does not match any of the WHEN part, then the WHEN OTHERS part will be chosen.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bcd IS PORT (
I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Segs: OUT std_logic_vector (1 TO 7));
Microprocessor Design – Principles and Practices with VHDL |
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Chapter 3 − Combinational Circuits |
Page 23 of 26 |
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END bcd; |
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ARCHITECTURE Behavioral OF bcd IS |
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PROCESS(I) |
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CASE I IS |
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WHEN "0000" => Segs <= "1111110"; |
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WHEN "0001" => Segs <= "0110000"; |
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WHEN "0010" => Segs <= "1101101"; |
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WHEN "0011" => Segs <= "1111001"; |
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WHEN "0100" => Segs <= "0110011"; |
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WHEN "0101" => Segs <= "1011011"; |
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WHEN "0110" => Segs <= "1011111"; |
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WHEN "0111" => Segs <= "1110000"; |
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WHEN "1000" => Segs <= "1111111"; |
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WHEN "1001" => Segs <= "1110011"; |
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WHEN OTHERS => Segs <= "0000000"; |
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END CASE; |
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END PROCESS; |
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END Behavioral; |
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Figure 10. Behavioral VHDL description of the BCD to 7-segment decoder. |
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3.8Summary Checklist
Binary number
Microprocessor Design – Principles and Practices with VHDL |
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Chapter 3 − Combinational Circuits |
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3.9Exercises
3.1 Use a truth table to show that (w |
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z) = (w x) (y z) = (((w x) y) z). |
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3.2Use Boolean algebra to derive the 1-minterms for the equation F = w x y z. Answer
F = w x y z
=(wx + w'x' ) y z
=[(wx + w'x' )y + (wx + w'x' )' y' ] z + [(wx + w'x' )y + (wx + w'x' )' y' ]' z'
=wxyz + w'x'yz + (wx)' (w'x' )'y'z + [(wx + w'x' )y + (wx + w'x' )' y' ]' z'
=m15 + m3 + (w'+x' )(w+x)y'z + [(wx + w'x' )y + (wx + w'x' )' y' ]' z'
=m15 + m3 + w'xy'z + wx'y'z + [(wx + w'x' )y + (wx + w'x' )' y' ]' z'
=m15 + m3 + m5 + m9 + [(wx + w'x' ) y]' [(wx + w'x' )' y' ]' z'
=m15 + m3 + m5 + m9 + [(wx + w'x' )' + y' ] [(wx + w'x' )+ y] z'
=m15 + m3 + m5 + m9 + [(wx)' (w'x' )' + y' ] [wxz' + w'x' z' + yz' ]
=m15 + m3 + m5 + m9 + [(w'+x' )(w+x) + y' ] [wxz' + w'x' z' + yz' ]
=m15 + m3 + m5 + m9 + [w'x + wx' + y' ] [wxz' + w'x' z' + yz' ]
=m15 + m3 + m5 + m9 + w'xyz' + wx'yz' + wxy'z' + w'x'y'z'
=m15 + m3 + m5 + m9 + m6 + m10 + m12 + m0
3.3Use Boolean algebra to show that the following circuit is equivalent to a 2-input XOR gate.
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Answer
From the circuit, we get F = (((xy)'x)' ((xy)'y)' )'.
F= [((xy)'x)' ((xy)'y)' ]'
=((xy)'x) + ((xy)'y)
=(x' + y' )x + (x' + y' )y
=xx' + xy' + x'y + y'y
=xy' + x'y
=x y
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Chapter 3 − Combinational Circuits |
Page 25 of 26 |
3.4Convert the following full adder circuit to use only eleven 2-input NAND gates.
xy
cout
cin
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Recall that wx + yz = ((wx)' (yz)')'. Furthermore, x y |
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z = x y z and x y = (x'y' + xy). |
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cout 
cin
s
3.5Perform a timing analysis of the circuit shown in Figure 5(c) to see that the circuit does not produce any glitches.
Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/17/2003 5:56 PM |
Chapter 3 − Combinational Circuits
Index
× . See Don’t cares. 7-segment decoder, 15
A
Analysis
combinational circuits, of, 2
C
Characterize, 11 Combinational circuit
analysis. See Analysis of. minimization. See Minimization of. synthesis. See Synthesis of.
Combinational circuits, 2
D
Don’t cares, 13
E
Essential prime implicant, 11
G
Glitch, 15
H
Hazard, 15
K
Karnaugh-map. See K-map.
K-map, 8
M
Minimal cover, 11 Minimization
combinational circuits, of, 8
Page 26 of 26
Minterms, 9
N
NAND gate, 5
NOR gate, 5
P
Prime implicant, 11
Process block. See VHDL:statement:process block. Product term, 11
Q
Quine-McCluskey method, 13
S
Sensitivity list. See VHDL:sensitivity list. Subcube, 10
Synthesis
combinational circuits, of, 4
T
Tabulation method, 13
See also Quine-McCluskey method.
Technology mapping, 5
V
VHDL, 18
behavioral level, 18, 21 dataflow level, 18, 21 sensitivity list, 21 structural level, 18
VHDL code
7-segment decoder, 18, 21 VHDL statement
Process block, 18, 21
Microprocessor Design – Principles and Practices with VHDL |
Last updated 7/17/2003 5:56 PM |