Digital Design VHDL Laboratory

2.VHDL Behavior and Structure models

pepe, 5/23/96

Another example of behavior modeling is again the D flip flop construction using two D latches which was illustrated earlier in Figure 2-5. Listing 2-4, however, shows the construction of a D flip flop without using any D latches. By using the behavior modeling technique, the VHDL code length was reduced drastically. A circuit similar to a D flip flop in size would be tedious to describe totally described in a structural model.

--

-- behavior modeling of D latch

--

entity rdffb is
port(
reset: in bit;	-- reset signal
c, d: in bit;	-- input data, c=clock, d=data

q, nq: out bit ); -- output q and not q end rdffb;

-- behavior model

architecture behavior of rdffb is begin

behavior: process (c, reset) begin

if reset='1' then

q	<= '0';
nq	<= '1';

elsif (c='1' and c'event) then

q	<= d;
nq	<= not d;
end if;

end process behavior;

end behavior;

Listing 2-4. D Flip Flop Behavior Modeling

2.2 Problems

1)Implement a D latch with reset using VHDL structure modeling. Demonstrate its functionality in the Cypress NOVA simulator by resetting the circuit, latching in a high value, and resetting again at the next clock cycle when the input is kept high. Save the simulation session to a stimulus file (*.SIM) and trace file (*.PSD) using the NOVA FILE menu items.

2)A T flip flop can be defined as a flip flop that toggles the output at the edge of the clock cycle, for example, rising or falling edge. Implement T flip flop behaviorally. Again, save the simulation session in both stimulus file and trace file.

3)Implement an RS flip flop using an AND gate, and model it structurally. Demonstrate and show its functionality.

4)In VHDL, implement the circuit described below using two D flip flops with /RESET input. The circuit should first be implemented in a behavior model and, then, in a structure model. Show the functionality using the VHDL simulator. (Hint: Utilize /RESET input).

INPUT:	Two input lines, A and B.
OUTPUT:	One output C.
CONDITIONS:		a) The output goes to 1 on every positive transition of the A line.
		b) The output goes to 0 on every positive transition of the B line.

c) The output must be capable of set to 1 again after it being to 0. d) Input B takes precedence over Input A to affect the output.

18	Copyright 1996, CERL / EE, V1.00