Frame D.Printed circuit board and connector impedance matching using complex conjugation.2004

PRINTED CIRCUIT BOARD AND CONNECTOR IMPEDANCE MATCHING

USING COMPLEX CONJUGATION

by

David W. Frame

A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in Technology

ARIZONA STATE UNIVERSITY

December 2004

PRINTED CIRCUIT BOARD AND CONNECTOR IMPEDANCE MATCHING

USING COMPLEX CONJUGATION by

David W. Frame

has been approved December 2004

APPROVED:

, Chair

Supervisory Committee

ACCEPTED:

Department Chair

Dean, Division of Graduate Studies

ABSTRACT

This thesis analyzes two methods for mitigating connector parasitics in high speed, multiple printed circuit board, digital interconnects. In these methods, basic engineering approaches are employed to calculate compensating parasitics to add to the interconnect. Simulations provide correlation to prove the effectiveness of these techniques.

One method, Complex Conjugation, uses complex mathematics in an array of formulas to calculate the complex compensation needed for the channel. This method gives a much more in-depth analysis of losses and phase relationships between current and voltage. In contrast, the second, “Pot Hole” method is mathematically simple as well as straight forward to employ but ignores both losses and phase relationships. The complications created by the use of complex mathematics are avoided by this method, thus, allowing for faster solutions. The solutions have proven to provide identical parasitic compensation above certain frequencies.

In the interest of design efficiency, the simpler “Pot Hole” method should be used as a standard design tool. Connector parasitic mitigation is not improved by the application of the Complex Conjugation methodology. As speed increases, the need to compensate for phase velocity mismatches and to account for all losses will become imperative. However, these should to be tracked in a separate analysis, using tools that are best suited for this purpose.

This thesis proves that the use of Complex Conjugation is not required to compensate for connector parasitics. The decreased design time associated with this discovery can be used to reduce time to market, or allow time to further analyze other

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aspects of the design. In either case, engineering efficiency will be improved, providing increased system reliability and increased profit.

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This work is dedicated to my loving wife Jan.

The Beach Boys sang, “God only knows what I'd be without you” I do not know the answer, and I’m very happy for this ignorance.

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ACKNOWLEDGEMENTS

I would like to thank my advisor Dr. Barbra Gannod for her patience and guidance with this thesis. I would also like to thank the rest of my committee for their help and guidance. Additionally, I am indebted to countless engineers at Intel Corporation who have listened to my ideas and provided feedback. In particular, I thank Richard Mellitz for providing the inspiration for this topic, and Karl Mauritz, who taught me so much more than just signal integrity.

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TABLE OF CONTENTS
	Page
LIST OF TABLES.......................................................................................................	ix
LIST OF FIGURES ......................................................................................................	x
CHAPTER
I. INTRODUCTION .........................................................................................	1
A. Motivation........................................................................................	3
1)Problem Statement:........................................................................	3
2)Objective:.......................................................................................	4
3)Scope: ............................................................................................	4
4)Assumptions: .................................................................................	4
5)Limitations:....................................................................................	4
6)Contributions: ................................................................................	5
II. BACKGROUND..........................................................................................	6
A. Lumped vs. Distributed....................................................................	9
B. Transmission Line Impedance .......................................................	10
C. Bandwidth of Digital Signals .........................................................	12
III. ANALYSIS...............................................................................................	14
A. Circuitry .........................................................................................	14
B. “Pot Hole” Solution........................................................................	14
C. Complex Conjugation Solution......................................................	17
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CHAPTER	Page
IV. SIMULATION .........................................................................................	24
A. Setup...............................................................................................	24
B. Results ............................................................................................	25
V. CONCLUSIONS........................................................................................	31
REFERENCES ...........................................................................................................	33
APPENDIX
A. HSPICE CODE ..........................................................................................	36

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LIST OF TABLES
TABLE	Page
I. PARASITIC PARAMETERS FOR AMPMODU SYSTEM 50 CONNECTOR	...................... 16
II. PCB PARAMETERS ..................................................................................................	18

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LIST OF FIGURES
FIGURE	Page
Fig. 1. MPEG non-linear vs. Graphics linear memory access where w is the width of the
display (and the display buffer). ...........................................................................	2
Fig. 2. PCB trace profile of capacitive load..................................................................	6
Fig. 3. Capacitive load with equalizing parasitic inductance........................................	7
Fig. 4 Transmission line section .................................................................................	10
Fig. 5. PCB cross-section............................................................................................	11
Fig. 6. Progression of frequency components to make a square wave. ......................	13
Fig. 7. Circuit for analysis and simulation..................................................................	14
Fig. 8. Dimensions of the microstrip transmission line. .............................................	15
Fig. 9. Magnitude of Z (Zmag) approaches (sqrt(L/C) for Trace. ................................	21
Fig. 10. Magnitude of Z (Zmag) approaches (sqrt(L/C) for Connector........................	22
Fig. 11. Simulation Schematic....................................................................................	24
Fig. 12. Filter schematic..............................................................................................	25
Fig. 13. Filtered and unfiltered output from driver with simple load. ........................	26
Fig. 14. Initial input waveform. ..................................................................................	27
Fig. 15. Input waveform with connector.....................................................................	28
Fig. 16. Connector perturbation with 10ps rise time highlighted. ..............................	29
Fig. 17. Connector perturbation with a 1ns rise time highlighted. .............................	29
Fig. 18. Input waveform with connector and mitigation. ...........................................	30

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