Voltage Regulator Input
The VBATT pin (pin 25) is the 12-volt input to the internal voltage regulator, with the ground return provided through the two VSSD pins (pins 3 and 31). In automotive applications, the VBATT pin can be connected directly to the vehicle’s battery, allowing the internal regulator to provide the 5-volt supply for the MCU.
However, voltage transients exceeding the maximum specifications of the VBATT pin are sometimes encountered in automotive applications. For this reason, additional components may be necessary to ensure the VBATT pin is not damaged if such a situation occurs. The circuit includes an example transient protection network between the vehicle’s battery and the VBATT pin to protect against this. To help reduce the effects of temporary fluctuations in the 12-volt supply caused by noise and by changes in loading on the vehicle's electrical system, a large capacitor (10 µF or greater) can be placed between the 12-volt supply and ground. If high frequency noise on the 12-volt supply is a problem, the user also can add decoupling capacitors between VBATT and VSSD. Ceramic or polystyrene capacitors should be used to provide noise rejection over a wide frequency range. If decoupling capacitors on the 12-volt supply are used, they should be placed as close to the MCU pins as possible.
The VIGN pin (pin 29) is used to tell the power supply control logic when to enable the primary regulator.
The VIGN pin is an input pin designed to operate over an input voltage range equal to the supply voltage at the VBATT pin. If a rising edge is detected at the VIGN pin and the primary regulator is in standby mode, the primary regulator will transition to the normal operating mode, powering up the MCU. This feature can be
useful in those applications where a component or module is required to remain powered up but inactive for long periods. This is common in the automotive environment, where a system may be required to operate whether the vehicle ignition is switched on or not. In this type of application, the VBATT pin can be
connected to a constant 12-volt supply while the VIGN pin is connected to a switched 12-volt supply. Once the switched supply is turned off, the application software can put the primary regulator into standby mode, powering the MCU down to conserve energy until operation is again required. When the switched supply is
turned back on, the rising edge at the VIGNpin will cause the primary regulator to exit standby mode and reactivate the MCU. This type of operation allows the MCU to conserve energy when activity is not required, but to be reactivated immediately when necessary.
Voltage Regulator Output
As described in POWER SUPPLY ARCHITECTURE, in addition to supplying 5 volts to the digital circuitry of the MCU internally, the output of the on-chip voltage regulator is connected to the two VDD pins (pins 30 and 4) of the MCU to allow external stabilization and decoupling of the power supply output. To ensure a stable 5-volt supply from the primary voltage regulator on the MC68HC705V8 and MC68HC05V7, a 10 µF tantalum or electrolytic bulk capacitor should be connected between pins 30 and 31 (VDD and VSSD, respectively). This capacitor should be placed between this pair of VDD/VSSD pins since they are physically closer to the output of the voltage regulation circuit on the device than the other pair of VDD/VSSD pins (pins 4 and 3, respectively). This capacitor should be positioned as close to the VDD/VSS pins as possible to maximize its effect.
High frequency decoupling capacitors (ceramic or polystyrene) should be placed between both pairs of VDD/VSSD pins, also positioned as close to the MCU as possible (even closer than the bulk capacitor at pins 30 and 31). These are necessary to help reduce radiated RF emissions as well as to reduce high
frequency noise on the 5-volt supply. The example in Figure 2 has .1 µF capacitors between each pair of VDD/VSSD pins for external decoupling. Because pin 4 is connected internally to the output of the primary voltage regulator through a resistance of approximately 40 Ω and the inductance of the bond wire at each
pin is approximately 4 nH, the self-resonance of the decoupling network between pins 3 and 4 may be too low. In this case, a smaller capacitor (470 ρF to .01 µF) can be added in parallel to the .1 µF between these pins to increase the bandwidth of the decoupling network. If so, the smaller capacitor should be placed closest to the MCU. The VSSD pins should be connected in the application to ensure an adequate low-impedance ground return for the system. The effect of not connecting the VDD pins is not yet known, and it is currently recommended that they be connected as well.
In the example circuit in Figure 2, the 5 volts available from the VDD pins are connected to the VCCA pin (pin 40) to supply 5 volts to the analog circuitry. In both the MC68HC705V8 and the MC68HC05V7, the analog and digital supplies are not connected internally, so the 5 volts for the analog circuitry must be supplied externally. As with any externally supplied power source, an appropriate decoupling capacitor has been placed between VCCA and the adjacent A/D subsystem analog ground return (VSSA1, pin 41). A separate ground return (VSSA2, pin 22) is provided for the SAE J1850 analog subsystem. To power additional external circuitry from the on-chip regulator, either of the VDD pins can be used as the source of 5 volts. However, when possible, the VDD pin closest to the on-chip regulator (pin 30) should be used as a 5-volt source for external components. This improves the regulator's response to the additional fluctuations in the 5-volt supply loading caused by supplying the external components.
Also shown in Figure 2 is a simple power-on reset (POR) circuit connected to the reset pin (RST, pin 7) to provide a time delay between full activation of the primary regulator and external release of the RST pin. Although an external POR circuit is not required when the LVR mask option is selected, it does allow time
for the VDD supply to stabilize before the RST pin is released externally. If the LVR option is not selected, the user should certainly consider some sort of external POR/LVR circuitry to prevent unpredictable operation during power-up, power-down, and brown-out situations.
Рисунок 39 – Interfacing the MC68HC705J1A to 9356/9366 EEPROMs
Рисунок 40 – Evaluation Board: Memories
Рисунок 41 – Evaluation Board: Power, Crystal Oscillator, Clock Distribution and Power Supply Shutdown
Рисунок 42 – Evaluation Board: Push Buttons, LEDs, Reset and Serial Interface
Рисунок 43 – Цифровой диктофон (Digital Sound Recorder with AVR and DataFlash: Microcontroller and Memory Circuit Diagram)
The user can control the sound system with three pushbuttons, called “Erase”, “Record” and “Playback”. If the pushbuttons are not pressed, the internal pull-up resistors provide VCCat PD0 - PD2. Pushing a button pulls the input line to GND. As feedback for the user, an LED indicates the status of the system.
The DataFlash is directly connected to the AVR microcontroller using the SPI bus. In case the ISP feature is used to reprogram the AVR, the pull-up resistor on the Chip Select line (CS) prevents the DataFlash from going active. If the ISP feature is not used, this resistor can be omitted.
The analog voltage, AVCC, is connected to VCCby an RC low-pass filter. The reference voltage is set to AVCC.
The oscillator crystal with two 22 pF decoupling capacitors generates the system clock.
Рисунок 44 – Цифровой диктофон (Digital Sound Recorder with AVR and DataFlash: Microphone and Speaker Circuit Diagram)
The microphone amplifier is a simple inverting amplifier. The gain is set with R1 and R9 (gain = R1 / R9). R4 is used to power the microphone and C1 blocks any DC component to the amplifier. R2 and R3 set the offset. R5 and C8 form a simple first order low-pass filter. In addition R5 protects the amplifier from any damage if the output is short circuited.
The speaker circuit consists of a 5th-order, low-pass Chebychev filter and a unary-gain amplifier.
The filter is made up by two stagger-tuned, 2nd-order Chebychev filters (R6, R7, R8, C2, C7 and R7, R10, R11, C9, C5) and a passive 1st-order filter (R11, C4). The cut-off frequencies of these three filters are slightly shifted against each other (“staggered”) to limit passband ripple of the whole filter circuit. The overall cut-off frequency is set to 4000 Hz, which is roughly one-quarter of the PWM frequency (15,686 Hz).
The unary-gain amplifier prevents the circuit from getting feedback from the output. C3 blocks any DC component to the speaker.
Рисунок 45 – Макетно-отладочная плата. Принципиальная схема
Рисунок 46 – Макетно-отладочная плата. Принципиальная схема (продолжение)
Рисунок 47 – Контроллер-конструктор
Управление LCD дисплеем (DIRECT DRIVE OF LCD DISPLAYS):
The
heart of the application is the LCD direct drive software, of course.
The LCD drive is based on a timer
interrupt that runs every 10 ms (100-Hz plane drive frequency.) This timer interrupt must occur on time since
any deviation causes a net DC voltage to be applied to the liquid crystal. For this reason, the timer interrupt always has priority over the other sections of the code. Also, since math can cause a variable execution length, all the math for the LCD service is performed in advance. Immediately after the timer interrupt is acknowledged, the new data is copied out to the port pins. The service routine then sets about calculating the data for the next interrupt. This ensures that the only variable in the placement of edges at the LCD pins is the interrupt latency.
The LCD and real time clock are driven by timer T1. When a timer interrupt is issued, the contents of the registers are copied to the ports. The Z8 then performs the math required to set up the next phase.
The current phase is set by the values of P37 and an offset holding register, PHASE_PTR. The value of PHASE_PTR switches from 1 to 0 at each cycle, and points to the data to be sent to plane 1 or plane 2. As described in the first section, the value of P37 causes inversion on the common planes at alternating cycles. The common plane voltages are generated by using the XOR function to flip the appropriate pins for each cycle. The current value of the port 3 outputs are stored in an image register to ensure that the XOR function reads valid data levels and to allow the next plane state to be set up on the prior cycle. The next state is simply created by taking the XOR of the current value with a number that represents the pins that should flip for this cycle. The number is then updated to change the pins that flip for the next cycle. Because the pins in question are P34, P35 and P37, the magic numbers are 0x30 and 0x80, alternately. The easiest way to flip the number between 0x30 and 0x80 is by alternately adding 0x50 (80 decimal) and 0xB0 (-80 decimal.) Storing the adder value in a register results in the sign flipping for each cycle just by taking its two’s complement (COM and then INC.)
Рисунок 48 – Цепь управления (LCD Direct Drive Demo Circuit)
Multiple Backplanes
In
order to reduce the number of control lines required, for large
segment counts, modern LCD display panels are usually built with more
than one backplane. This is done by splitting the backplane glass
into several conductors and connecting more than one segment to each
control pin. Then, by placing a signal on the common pins as well as
the segment pins, the segments can be toggled independently.
Figure 3aillustrates how two segments can share a segment driver line and Figure 4 shows the signals that
would be generated to drive the two segments.
In this example, segment A (the top of the character) would be ON and segment G (the bar across the middle) would be OFF. The two common planes drive an alternating signal with periods of zero between each high and low drive pulse and the planes out of phase with each other. The common signal pin is then driven with the data for both pins, the data for common 1, data for common 2, inverted data for common 1 and inverted data for common 2.
The resulting waveforms at each segment are shown at the bottom of Figure 4. The Root Mean Squared (RMS)
value of the signal on segment A is larger than the initial voltage of the liquid crystal so it appears dark while the RMS voltage across segment G is below the threshold so the segment is clear.
It is important to keep each segment toggling quickly enough to prevent noticeable flicker. The common planes must toggle twice as fast in a two-plane configuration, four times as fast in a four plane, and so forth. Obviously, as the number of backplanes goes up, the speed of the driving processor must also increase. This sets up a trade off between speed of the controller and complexity of the glass on one side and pin count on the other.
Рисунок 49 – PIC17C4X EXTERNAL RAM SCHEMATIC
Рисунок 50 – Клавиатура (HC05 MCU Keypad Decoding Techniques Using the MC68HC705J1A)