1. U‑boot‑1.1.1/board/rm9200/rm9200.C – номер архитектуры

Нужен номер архитектуры на этапе загрузки ядра Linux.

Листинг программы, отображающий изменения в исходном тексте для изменения номера архитектуры :

int board_init (void)

{

…..

/* arch number of AT91RM9200DK-Board */

// gd->bd->bi_arch_number = 251; // default as MACH_TYPE_AT91

gd->bd->bi_arch_number = 262; // veter - DK

/* adress of boot parameters */

….

}

3. U‑boot‑1.1.1/include/configs/rm9200.H – файл конфигурации платы

Изменения, вносимые в исходный текст u‑boot‑1.1.1/include/configs/RM9200.h

Результирующий RM9200.hфайл, который можно использовать как базовый конфигурационный файл, с предварительными рабочими настройками.

Описать кратко содержание данного файла, что и зачем там написано. Листинг файла вынести в приложение.

Листинг программы, отображающий изменения в исходном тексте – конфигурационный файл:

/*

* Configuation settings for the RM9200 board.

*

* (c) Copyright 2004 Roman Avramenko <[e-mail]>

* Industrial Monitoring Systems, Ltd

*

* See file CREDITS for list of people who contributed to this

* project.

*

* This program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of

* the License, or (at your option) any later version.

*

* This program is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License

* along with this program; if not, write to the Free Software

* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

* MA 02111-1307 USA

*/

#ifndef __CONFIG_H

#define __CONFIG_H

#define CONFIG_EVM9200

#define MASTER_CLOCK_45

//#define MASTER_CLOCK_60 /* Master clock 60Mhz */

//#define DRAM_SIZE_16MB

#define DRAM_SIZE_32MB

#define MORECORE_FAILURE 0

/* CHECK FIRST: Board and revision specific settings */

#undef CFG_ENV_IS_IN_DATAFLASH

#undef CFG_ENV_IS_IN_NVRAM

#ifdef CONFIG_EVM9200

#define CFG_ENV_IS_IN_FLASH

#undef CONFIG_HARD_I2C

#undef CFG_ENV_IS_IN_EEPROM

#else /* CONFIG_EVM9200 */

#undef CFG_ENV_IS_IN_FLASH

#undef CFG_ENV_IS_IN_EEPROM

#define CONFIG_HARD_I2C 1 /* Hardware I2C interface */

#define CFG_ENV_IS_IN_EEPROM 1

#endif

/*

* If we are developing, we might want to start armboot from ram

* so we MUST NOT initialize critical regs like mem-timing ...

*/

#define CONFIG_INIT_CRITICAL /* undef for developing */

//#define CONFIG_ENV_OVERWRITE /* Let's change ethaddr */

#define CONFIG_MISC_INIT_R /* Needed to init MAC address setting */

/* ARM asynchronous clock */

#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal(18432000/4*39) */

#ifdef MASTER_CLOCK_45 /* Master clock 45Mhz */

#define AT91C_MASTER_CLOCK 44928000 /* peripheral clock (AT91C_MAIN_CLOCK/3)*/

#else /* MASTER_CLOCK_45 */

#ifdef MASTER_CLOCK_60

#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MAIN_CLOCK/3) */

#else /* MASTER_CLOCK_60 */

#error Master clock must be defined

#endif

#endif

#define AT91_SLOW_CLOCK 32768 /* slow clock */

#define CONFIG_RM9200 1 /* on a RM9200 Board */

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */

#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */

#define CONFIG_SETUP_MEMORY_TAGS 1

#define CONFIG_INITRD_TAG 1

/*

* Size of malloc() pool

*/

#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)

#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */

#define CONFIG_BAUDRATE 115200

#ifdef MASTER_CLOCK_45 /* Master clock 45Mhz */

#define CFG_AT91C_BRGR_DIVISOR 24

#else /* MASTER_CLOCK_45 */

#ifdef MASTER_CLOCK_60

#define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */

#endif /* MASTER_CLOCK_60 */

#endif

/*

* Hardware drivers

*/

#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */

#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */

#define CONFIG_BOOTDELAY 3

//#define CONFIG_BOOTCOMMAND "bootm 10020000"

//#define CONFIG_BOOTCOMMAND "bootm 20007fc0"

//#define CONFIG_BOOTCOMMAND "tftp 20007fc0 uImage; bootm 20007fc0"

//#define CONFIG_BOOTCOMMAND "tftp 20008000 uImage; bootm 20008000"

//#define CONFIG_BOOTCOMMAND "cp.b C002A000 20A00000 200000; bootm 20A00000"

//#define CONFIG_BOOTCOMMAND "cp.b C002A000 20008000 200000; bootm 20008000"

#define CONFIG_BOOTCOMMAND "cp.b C002A000 20A00000 200000; cp.b C0160000 20C00000 600000; bootm 20A00000 20C00000"

//#define CONFIG_AUTOBOOT_KEYED 1

#undef CONFIG_AUTOBOOT_KEYED

#define CONFIG_AUTOBOOT_DELAY_STR "uboot"

#define CONFIG_AUTOBOOT_STOP_STR "uboot"

#define CONFIG_AUTOBOOT_STOP_STR2 "uboot"

#define CONFIG_ZERO_BOOTDELAY_CHECK 1

//#define CONFIG_BOOTARGS "root=/dev/ram rw initrd=0x20288000,0x500000 ramdisk_size=8000 mtdparts=AT45DB642.spi0:0x2A000(boot)ro,0x136000(kernel)ro,0x200300(initrd)ro,-(filesystem) console=ttyS0,115200 mem=32M"

//#define CONFIG_BOOTARGS "root=/dev/ram0 rw initrd=0x20288000,0x500000 ramdisk_size=5000 mtdparts=AT45DB642.spi0:0x2A000(boot)ro,0x136000(kernel)ro,0x200300(initrd)ro,-(filesystem) console=ttyS0,115200 mem=64M"

#define CONFIG_BOOTARGS "root=/dev/ram rw mtdparts=AT45DB642.spi0:0x2A000(boot)ro,0x136000(kernel)ro,0x200300(initrd)ro,-(filesystem) console=ttyS0,115200 mem=64M"

//#ifdef CONFIG_EVM9200

//#define CONFIG_NETMASK 255.0.0.0

//#define CONFIG_IPADDR 10.0.0.2

//#define CONFIG_ETHADDR 12:34:56:78:9A:BC

//#define CONFIG_SERVERIP 10.0.0.1

//#define CONFIG_BOOTFILE "u-boot.bin.gz"

#ifdef CONFIG_EVM9200

#define CONFIG_NETMASK 255.255.255.0

#define CONFIG_IPADDR 192.168.1.123

#define CONFIG_ETHADDR 00:12:34:56:78:9A

#define CONFIG_SERVERIP 192.168.1.1

#define CONFIG_BOOTFILE "uImage"

#endif /* CONFIG_EVM9200 */

/* #define CONFIG_ENV_OVERWRITE 1 */

#ifdef CONFIG_EVM9200

#define CONFIG_COMMANDS \

((CONFIG_CMD_DFL | \

CFG_CMD_NET | \

CFG_CMD_BDI | \

CFG_CMD_PING \

) \

& ~(CFG_CMD_FPGA | \

CFG_CMD_NAND \

) \

)

#define CFG_LONGHELP

/*#else

#define CONFIG_COMMANDS \

(CONFIG_CMD_DFL | \

CFG_CMD_NET | \

CFG_CMD_PING | \

CFG_CMD_I2C | \

CFG_CMD_EEPROM \

& ~(CFG_CMD_BDI | \

CFG_CMD_FPGA | \

CFG_CMD_NAND \

) \

)

*/

#endif

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */

#include <cmd_confdefs.h>

#define CFG_HUSH_PARSER

#define CFG_PROMPT_HUSH_PS2 "> "

#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */

#define SECTORSIZE 512

#define ADDR_COLUMN 1

#define ADDR_PAGE 2

#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN 0x00

#define NAND_MAX_FLOORS 1

#define NAND_MAX_CHIPS 1

#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */

#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */

#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)

#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)

#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)

#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)

#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)

#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))

/* the following are NOP's in our implementation */

#define NAND_CTL_CLRALE(nandptr)

#define NAND_CTL_SETALE(nandptr)

#define NAND_CTL_CLRCLE(nandptr)

#define NAND_CTL_SETCLE(nandptr)

#define CONFIG_NR_DRAM_BANKS 1

#define PHYS_SDRAM 0x20000000

#ifdef DRAM_SIZE_16MB

#define PHYS_SDRAM_SIZE 0x01000000 /* 16 megs */

#else

//#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */

#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */

#endif /* DRAM_SIZE_16MB */

#define CFG_MEMTEST_START PHYS_SDRAM

#define CFG_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE - 1024*1024 - CFG_MALLOC_LEN)

#define CFG_ALT_MEMTEST

//#define CONFIG_DRIVER_ETHER

//#define CONFIG_PHY_IS_RTL8201

#define CONFIG_DRIVER_ETHER

//#define CONFIG_PHY_IS_RTL8201

#define CONFIG_PHY_IS_LXT972

#ifdef CONFIG_EVM9200

#define CFG_PHY_MDI_ADDRESS (0x1F ^ 0x02)

#else

#define CFG_PHY_MDI_ADDRESS 1

#endif

#define CONFIG_NET_RETRY_COUNT 20

#undef CONFIG_AT91C_USE_RMII

/*#define CONFIG_AT91C_USE_RMII */

#undef CONFIG_HAS_DATAFLASH

#define CONFIG_HAS_DATAFLASH 1 /* veter */

#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)

#define CFG_MAX_DATAFLASH_BANKS 2

#define CFG_MAX_DATAFLASH_PAGES 16384

#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */

#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */

#define PHYS_FLASH 0x10000000

//#define PHYS_FLASH_SIZE 0x00400000 /* 4 Megs main flash */

#define CFG_FLASH_BASE PHYS_FLASH

#define CFG_MAX_FLASH_BANKS 1

#define CFG_MAX_FLASH_SECT 256

#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */

#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */

#undef CFG_FLASH_CFI

#define CFG_I2C_SPEED 100000

#define CFG_I2C_SLAVE 0xFE

#define CFG_I2C_EEPROM_ADDR 0x50

#define CFG_I2C_EEPROM_ADDR_LEN 1

#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* AT24C08 EEPROM */

#define CFG_ENV_IS_IN_DATAFLASH /* veter */

#if defined(CFG_ENV_IS_IN_DATAFLASH)

//#define CFG_ENV_OFFSET 0x20000

#define CFG_ENV_OFFSET 0x28000

#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)

#define CFG_ENV_SIZE 0x2000 /* 0x8000 */

#elif defined(CFG_ENV_IS_IN_FLASH)

#ifdef CONFIG_EVM9200

#define CFG_ENV_ADDR (PHYS_FLASH + 0x1F0000)

#define CFG_ENV_SIZE 0x10000

#else /* CONFIG_EVM9200 */

#define CFG_ENV_ADDR (PHYS_FLASH + 0xE000)

#define CFG_ENV_SIZE 0x2000

#endif

#elif defined(CFG_ENV_IS_IN_EEPROM)

#define CFG_ENV_ADDR 0

#define CFG_ENV_OFFSET 0

#define CFG_ENV_SIZE 1024

#else

#define CFG_ENV_IS_NOWHERE

#define CFG_ENV_SIZE 0

#endif

#ifdef DRAM_SIZE_16MB

//#define CFG_LOAD_ADDR 0x20800000 /* default load address */

//#define CFG_LOAD_ADDR 0x20007fc0 /* default load address */

#define CFG_LOAD_ADDR 0x20008000 /* default load address */

#else

//#define CFG_LOAD_ADDR 0x21000000 /* default load address */

//#define CFG_LOAD_ADDR 0x20007fc0 /* default load address */

#define CFG_LOAD_ADDR 0x20008000 /* default load address */

#endif /* DRAM_SIZE_16MB */

#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */

#define CFG_U_BOOT_BASE (PHYS_FLASH + 0x10000)

#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */

#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }

#define CFG_PROMPT "u-boot -> " /* Monitor Command Prompt */

#define CFG_CBSIZE 256 /* Console I/O Buffer Size */

#define CFG_MAXARGS 16 /* max number of command args */

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

#ifndef __ASSEMBLY__

/*-----------------------------------------------------------------------

* Board specific extension for bd_info

*

* This structure is embedded in the global bd_info (bd_t) structure

* and can be used by the board specific code (eg board/...)

*/

struct bd_info_ext

{

/* helper variable for board environment handling

*

* env_crc_valid == 0 => uninitialised

* env_crc_valid > 0 => environment crc in flash is valid

* env_crc_valid < 0 => environment crc in flash is invalid

*/

int env_crc_valid;

};

#endif

#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to \

AT91C_TC_TIMER_DIV1_CLOCK */

#define CONFIG_STACKSIZE (32*1024) /* regular stack */

#ifdef CONFIG_USE_IRQ

#error CONFIG_USE_IRQ not supported

#endif

#endif

Это реально рабочий конфигурационный файл.

Нужно заметить еще один важный момент:

Значение #define CONFIG_ETHADDR 00:12:34:56:78:9A очень важно установить корректным, иначеLinuxне сможет “поднять интерфейс”