Allen and Holberg - CMOS Analog Circuit Design

Allen and Holberg - CMOS Analog Circuit Design

Page II.2-4

n- S/D LDD implant

Polysilicon	Photoresist
	FOX
	n-well
p- substrate
	(i)

LDD Diffusion

Polysilicon

FOX

n-well

p- substrate

	(j)
n+ Diffusion	p+ Diffusion	Polysilicon

FOX	FOX
	n-well
p- substrate

(k)

n+ Diffusion	p+ Diffusion	Polysilicon
		BPSG
	FOX	FOX
		n-well
p- substrate

(l)

Figure 2.1-5 The major CMOS process steps (cont'd).

Allen and Holberg - CMOS Analog Circuit Design

Page II.2-5

CVD oxide, Spin-on glass (SOG)	Metal 1
	BPSG
FOX	FOX
	n-well

p- substrate

(m)

Metal 2

Metal 1

BPSG

FOX	FOX
	n-well
p- substrate
	(n)

Metal 2

Metal 1

Passivation protection layer

	BPSG
FOX	FOX
	n-well
p- substrate

(o)

Figure 2.1-5 The major CMOS process steps (cont'd).

Allen and Holberg - CMOS Analog Circuit Design

Page II.2-6

Silicide/Salicide

Purpose

•Reduce interconnect resistance,

Polysilicide	Polysilicide
	Metal

Silicide

FOX

FOX

(a)

(b)

Figure 2.1-6 (a) Polycice structure and (b) Salicide structure.

Allen and Holberg - CMOS Analog Circuit Design

Page II.3-1

II.3 - PN JUNCTION

CONCEPT

Metallurgical Junction

p-type semiconductor

n-type semiconductor

iD

vD -

	Depletion
	region
p-type		n-type
semicon-		semicon-
ductor		ductor
iD	v	-
	+ D
	xd
xp		x
	0	xn

1.Doped atoms near the metallurgical junction lose their free carriers by diffusion.

2.As these fixed atoms lose their free carriers, they build up an electric field which opposes the diffusion mechanism.

3.Equilibrium conditions are reached when:

Current due to diffusion = Current due to electric field

Allen and Holberg - CMOS Analog Circuit Design

Page II.3-2

PN JUNCTION CHARACTERIZATION

	xd
xp	xn
p-type	n-type
semi-	semi-
con-	con-
ductor	ductor

iD

+vD -

Impurity concentration ( cm-3)

ND

x

0

-NA

Depletion charge concentration ( cm-3) qND

	xp		x
	0	xn
	-qNA
	Electric Field (V/cm)
			x

Eo

Potential (V)

φo− vD

x

xd

Allen and Holberg - CMOS Analog Circuit Design

Page II.3-3

SUMMARY OF PN JUNCTION ANALYSIS

Barrier potential-

φo =	kT	NAND
	q	ln	ni2

Depletion region widths-

NAND = Vt ln 2ni

	x n	=	2εsi(φo-vD)NA
			qND(NA+ND)

2εsi(φo-vD)ND x p = qND(NA+ND)

Depletion capacitance-

εsiqNAND

Cj = A 2(NA+ND) φ

1

o-vD

x 1 N

Cj0

= φo-vD

Breakdown voltage-
εsi(NA+ND)		2
BV =	2qNAND	Emax

Allen and Holberg - CMOS Analog Circuit Design

Page II.3-4

SUMMARY - CONTINUED

Current-Voltage Relationship-

	vD		Dppno		D nnp o
iD = Is exp -		1	where Is = qA	+
	Vt			Lp	Ln

25
20
iD 15
Is 10
5
0
-5 -4 -3 -2 -1 0	1	2	3	4

vD/Vt

0

-40	-30	-20	-10	0	10	20	30	40
				vD/Vt

Allen and Holberg - CMOS Analog Circuit Design

II.4-1

II.4 - MOS TRANSISTOR

ILLUSTRATION

Bulk	Source Gate Drain

Polysilicon

p+

n+

n+

n-channel

Channel

Length, L

p-substrate (bulk)

	Width,	W
Channel

tOX = 200 Angstroms = 0.2x10-7 meters = 0.02 m

TYPES OF TRANSISTORS

iD

Depletion	Enhancement
Mode	Mode

V (depletion)	VT (enhancement)	vGS
T

Allen and Holberg - CMOS Analog Circuit Design

II.4-2

CMOS TRANSISTOR

N-well process

n+

p-channel transistor

Polysilicon

L SiO2

source	(p+)	W	(p+)	source	(n+)
		drain

FOX

n-well

p- substrate

n-channel transistor

L

W		(n+)
	drain

p+

Figure 2.3-1 Physical structure of an n-channel and p-channel transistor in an n-well technology.

P-well process

• Inverse of the above.

Normally, all transistors are enhancement mode.

Allen and Holberg - CMOS Analog Circuit Design

II.4-3

TRANSISTOR OPERATING POLARTIES

	Type of Device	Polarity of	Polarity of vDS	Polarity of
		vGS and VT		vBULK
	n-channel, enhancement	+	+	Most negative
	n-channel, depletion	-	+	Most negative
	p-channel, enhancement	-	-	Most positive
	p-channel, depletion	+	-	Most positive

SYMBOLS FOR TRANSISTORS

Drain		Drain
Gate	Bulk	Gate
Source		Source/bulk
n-channel, enhance- n-channel, enhance-
ment, VBS ≠ 0		ment, bulk at most
		negative supply
Drain		Drain
Gate	Bulk	Gate
Source		Source/bulk
p-channel, enhance- p-channel, enhance-
ment, VBS ≠ 0		ment, bulk at most
		positive supply