60 RF CMOS POWER AMPLIFIERS:THEORY,DESIGN AND IMPLEMENTATION

variation technique similar to Doherty amplifier is employed. 2). Changing the gain of the input stage by varying the width of the input transistor. This might present different loading on the preceding stage, necessitating the use of a buffer stage. The first method would require two or more amplifiers in parallel, and the accurate implementation of micro-strip lines. Thus increasing both the area, and the footprint of the amplifier. The second method is the one utilized in this work. Varying the width of the transistor in the input stage is equivalent to having a number of transistors connected in parallel and switching them on and off using external control signals, depending on the required output power as shown in Figure 4.3(b).

By referring to Figure 4.1, instead of using a MOS switch to connect each parallel branch, the cascode transistor is acting as a non-ideal switch. The out- put power level is controlled via the voltages Ctr13, Ctrl2, Ctr11, and Ctr10. Figure 4.5 shows the variation of the output power and efficiency as a function of the number of fingers of the input transistor in the driver stage with unit transistor width.

In Figure 4.1, the inter-stage capacitance is adjusted to achieve matching.

Biasing for the input stage is done on-chip, while that of the output stage is controlled externally.

3.Implementation and Simulation Results

The detailed schematic of the core of the transistor is shown in Figure 4.6. The output transistor Ml is 1.44mm wide with length. In the layout, the transistor is partitioned into 4 separate transistors groups with substrate

A CMOS PA for Bluetooth

61

contacts surrounding each group of transistors as shown symbolically in Figure 4.7. In order to avoid any stability concerns, the ground nodes of the first and second stages are not connected together on chip. They have separate

62 RF CMOS POWER AMPLIFIERS:THEORY,DESIGN AND IMPLEMENTATION

nodes, and each is connected to a bond wire, then finally they are connected to the same PCB ground. This is a common practice in power amplifier design in order not to create inner loops and possible oscillations. The output transistor is located as close as possible to the output pad. The metal lines connecting the output node to the output pads are as wide as possible. The output pad is a simple metal pad with no ESD protection to minimize the pad capacitance, together with the fact that the normal pads supplied by the foundry has lim- ited current handling capability that is much smaller than the current delivered by the PA. Additionally, since the output node is the drain of the transistor rather than the gate, the fear of electrostatic discharge is minimal. A total of 10 ground pads are used to minimize the ground inductance. In general, a larger number should be used, but this comes at the expense of the total area. The complete layout is shown in Figure 4.8.

The output-matching network converts the 50-Ohm to the optimum load. Output matching is implemented off chip using a bond wire inductance and an external capacitance. Implementing the inductor on-chip dictates the use of a relatively wide inductor to handle the large output currents. This will increase the chip area, and will introduce a series parasitic resistance in series with the output load, consequently decreasing the efficiency. The choke coil (RFC) is implemented using micro-strip lines.

The core of the amplifier, together with bond-wire inductances, and the external matching elements are shown in Figure 4.9. The pads are represented by their parasitic capacitance only since no information was available on the substrate resistance. The interconnect resistances are also included.

A CMOS PA for Bluetooth

63

64 RF CMOS POWER AMPLIFIERS:THEORY,DES1GN AND IMPLEMENTATION

The extracted netlist of the PA is simulated using CADENCE (SPECTRE RF). Figure 4.10 shows the simulation results of the output power, and efficiency, together with the S-parameter of the amplifier. The simulation shows a maximum drain efficiency of 50% and PAE of 35%. The output power reaches 19dBm due to the effect of finite ground inductance, and large gate poly resis-