Chapter 3

Programmer’s Model

This chapter describes the ARM PrimeCell Audio CODEC Interface (PL040) registers and provides details needed when programming the microcontroller. It contains the following sections:

•About the programmer’s model on page 3-2

•Summary of PrimeCell ACI registers on page 3-3

•Register descriptions on page 3-4

•Interrupts on page 3-8.

ARM DDI 0146C

© Copyright ARM Limited 1999. All rights reserved.

3-1

Programmer’s Model

3.1About the programmer’s model

The base address of the PrimeCell ACI is not fixed, and may be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

The following locations are reserved, and must not be used during normal operation:

•locations at offsets +0x14–0x3c and +0x98–0xff are reserved for possible future extensions

•locations at offsets +0x40 through +0x94 are reserved for test purposes.

3-2

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0146C

Programmer’s Model

3.2Summary of PrimeCell ACI registers

The PrimeCell ACI registers are shown in Table -3-1.

Table 3-1 PrimeCell ACI register summary

	Address	Type	Width	Reset	Name	Description
				value
	ACI Base + 0x00	Read/	8	0x00	ACIDR	Data read or written from
		write				the AMBA APB interface
	ACI Base + 0x04	Read/	5	b---00000	ACICR	Control register
		write
	ACI Base + 0x08	Read	8	0x09	ACISR	Status register
	ACI Base + 0x0c	Read/	8	0x00	ACICDR_L	Clock divider register,
		write				LOW byte
	ACI Base + 0x10	Read/	2	b------00	ACICDR_H	Clock divider register,
		write				HIGH byte
	ACI Base + 0x14 - 0x3c	-	-	-	-	Reserved
	ACI Base + 0x40 - 0x94	-	-	-	-	Reserved (for test
						purposes)
	ACI Base + 0x98 - 0xff	-	-	-	-	Reserved

ARM DDI 0146C

© Copyright ARM Limited 1999. All rights reserved.

3-3