ARM PrimeCell Audio CODEC Interface (PL040) Signal Descriptions

A.3 Signals to pads

Table A-3 describes the signals from the PrimeCell ACI to input/output pads of the chip. It is the responsibility of the user to make proper use of the peripheral pins to meet the exact interface requirements.

				Table A-3 Pad signal descriptions
	Name	Type	Source/	Description
			destination
	ACIDATAIN	Input	Pad	Serial data input from off-chip CODEC.
	ACIDATAOUT	Output	Pad	Serial data output to off-chip CODEC.
				Active when TXEN bit is set, otherwise
				held LOW.
	ACIFSYNC	Output	Pad	Frame synchronization output pulse.
				A HIGH indicates the first bit (most
				significant bit) in the serial byte data
				frame. Both input and output serial bit
				streams are frame synchronous.
	ACIBITCLK	Output	Pad	Serial data bit clock output.
				Output data are synchronous to the
				ACIBITCLK rising edge. Input data are
				sampled on the falling edge of
				ACIBITCLK.

A-4

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0146C

Index

The items in this index are listed in alphabetic order, with symbols and numerics appearing at the end. The references given are to page numbers.

A

ACICDCNT		4-8
ACICDR	2-4, 3-6
ACICR	3-5
ACIDATAIN		2-9, 2-10
ACIDATAOUT 2-5, 2-8, 2-10, 4-7
ACIDR	3-4
ACIFSYNC		1-2, 2-5, 2-8, 4-7
ACIINTR	3-8, 3-9, 4-7
ACIRORINTR		4-7
ACIRXINTR		2-9, 3-8, 4-7
ACISR	3-6
ACITXINTR		2-9, 3-8, 3-9, 4-7

Advanced Microcontroller Bus

Architecture 1-2

AMBA
APB	1-2
APB interface		2-2, 2-4
ASB	2-4
compatibility		1-5
AMBA AHB 2-4
ATPG	4-3
Audio CODEC Interface 1-1, 2-1

Automatic test pattern generation 4-3

B

Base address	3-2
Big endian	1-5

Block diagram, PrimeCell ACI 2-3 BnRES 2-7, 3-5, 3-7, 4-5, 4-6

C

CDLDVAL 3-7

Clock divider
counter	3-7
register	2-8, 3-6
test count
enable		4-6
Compatibility, AMBA 1-5
Control register		2-8, 3-5

D

Data rate 1-4

Data register	2-8, 3-4
DECNIBBLE	4-6
DECUPPER	4-6

F

FIFO 2-2, 2-4, 2-8, 2-9, 3-9

receive	1-2, 2-5
transmit	1-2, 2-4

Frame synchronization frequency 1-4

ARM DDI 0146C

© Copyright ARM Limited 1998. All rights reserved.

Index-i

Index
Frequency
divider		2-4, 3-7
frame synchronization 1-4
I
Interface reset		2-7
Interrupt	2-9, 3-8
generation logic			2-5, 3-8
service routine			3-9
L
Little endian		1-5
LOOP	2-10, 3-5
Loopback test mode			2-10
N
nACIRST 2-7
Nibble decrement			4-6
O
Offsets	3-2

Overflow 2-9

P

PENABLE	4-5
PrimeCell ACI
block diagram		2-3
Integration Manual			1-5
operation	2-8
test harness		4-2
Programmer’s model			3-1
for test	4-1
PSEL 4-5

R

Receive
busy	3-6
enable	3-5
FIFO	1-2, 2-5
FIFO empty flag		3-6
FIFO full flag		3-6
interrupt enable		3-5
interrupt status		3-6
logic	2-5
overflow 2-9
REGCLK	4-5

Register
	clock divider				2-8, 3-6
	control			2-8, 3-5
	data		2-8, 3-4
	descriptions				3-4
	status		2-9, 3-6
	summary			3-3
	test		4-4
	test clock divider					4-8
	test clock enable					4-4
	test clock pre-scale counter 4-8
	test control				4-5
	test input stimulus					4-7
	test mode			4-6
	test output capture					4-7
	transmit shift				2-8
Registered clock mode						4-5
RIE	3-5, 3-8
RIS	3-6
RXBUSY			2-10, 3-6
RXEN		2-8, 2-10, 3-5
RXFE		3-6
RXFE/F			2-9
RXFF		3-6

S

Scan testing	4-3
SCANMODE	4-3

Status
flags	2-9
register	2-9, 3-6

Summary of registers 3-3 Synchronization frequency 1-4 Synchronizing registers and logic 2-6

System bus 2-4

System loopback testing 2-10

T

Test clock
divider register		4-8
enable	4-5
enable register		4-4
pre-scale counter register			4-8
Test control register		4-5
Test harness	4-2
Test input
select 4-5
stimulus register		4-7
Test mode
enable	4-6
register	4-6
Test output capture register			4-7
Test registers	4-4
and logic	2-6

Test reset		4-5
TESTCLKEN			4-5
TESTCOUNT			4-6
TESTDATAIN			4-7
TESTEN		4-6
Testing
scan		4-3
system loopback				2-10
TESTINPSEL			4-5, 4-7
TESTRST		4-5
TIE	3-5, 3-8
TIS	3-6
Transmit
busy		3-6
enable		3-5
FIFO		1-2, 2-4
FIFO empty flag				3-6
FIFO full flag				3-6
interrupt enable				3-5
interrupt status				3-6
logic		2-5
shift register			2-8
TXBUSY		2-10, 3-6
TXEN	2-8, 2-10, 3-5

TXFE 3-6

TXFE/F 2-9

TXFF 3-6

U

Underflow 2-9

Upper bit decrement 4-6

Index-ii

© Copyright ARM Limited 1998. All rights reserved.

ARM DDI 0146C