Functional Overview

2.2PrimeCell ACI functional description

The PrimeCell ACI block diagram is shown in Figure 2-1.

ACICLK

BnRES
PCLK
PSEL	AMBA
PENABLE	APB
PWRITE	interface
	and
PADDR[7:2]	register block
PWDATA[7:0]
PRDATA[7:0]
ACIRXINTR
ACIINTR
ACITXINTR
nACIRST
SCANMODE

		Frequency	ACIBITCLK
		divider
	Receive	Receive	ACIDATAIN
		shift
	FIFO
		register
	Interrupts	Bit	ACIFSYNC
	and FIFO
		counter
	level status
	Transmit	Transmit	ACIDATAOUT
		shift
	FIFO
		register

Figure 2-1 PrimeCell ACI block diagram

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Functional Overview

The functions of the PrimeCell ACI are described in the following sections:

•AMBA APB interface and register block

•Frequency divider

•Transmit FIFO

•Receive FIFO on page 2-5

•Transmit logic on page 2-5

•Receive logic on page 2-5

•Interrupt generation logic on page 2-5

•Synchronizing registers and logic on page 2-6

•Test registers and logic on page 2-6.

2.2.1AMBA APB interface and register block

The AMBA Advanced Peripheral Bus (APB) interface generates read and write decodes for accesses to status/control registers and transmit/receive FIFO memories.

The AMBA APB interface is a local secondary bus that provides a low-power extension to the higher bandwidth AMBA Advanced High-performance Bus (AHB) or AMBA Advanced System Bus (ASB) within the AMBA system hierarchy. The AMBA APB groups narrow-bus peripherals to avoid loading the system bus and provides an interface using memory-mapped registers that are accessed under programmed control.

The register block stores data values written or to be read across the AMBA APB interface.

2.2.2Frequency divider

The frequency divider contains free-running counters that generate the internal bit clock enable signals and the external ACIBITCLK output. The internal bit clock enables are a stream of pulses with a width of one ACICLK clock period. The internal bit clock enables are generated by dividing down from ACICLK according to the programmed divide value in ACICDR. ACIBITCLK provides timing information to the external CODEC. Data values transmitted to the CODEC are synchronous with the rising edge of ACIBITCLK and the received data values are sampled on the falling edge of

ACIBITCLK.

2.2.3Transmit FIFO

The transmit FIFO is an 8-bit wide memory buffer with a 16-byte depth. CPU data values written across the AMBA APB interface are stored in the FIFO until read out by the transmit logic.

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ARM DDI 0146C

Functional Overview

2.2.4Receive FIFO

The receive FIFO is an 8-bit wide memory buffer with a 16-byte depth. Received data values are stored in the receive FIFO by the receive logic until read out by the CPU via the AMBA APB interface.

2.2.5Transmit logic

The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream on ACIDATAOUT beginning with the Most Significant Bit (MSB) of the data, followed by successive bits and ending with the Least Significant Bit (LSB). The frame synchronization output ACIFSYNC is asserted HIGH for one period of ACIBITCLK (synchronous to the rising edge) to indicate the first bit (MSB) of the 8-bit data frame.

2.2.6Receive logic

The receive logic performs the serial-to-parallel conversion on the received bit stream, which is sampled on the falling edge of ACIBITCLK. The received word is then written to the receive FIFO. The receive and transmit data values are frame synchronous.

2.2.7Interrupt generation logic

Two individual maskable, active HIGH interrupts are generated by the PrimeCell ACI, and a combined interrupt output is also generated as an OR function of the individual interrupt requests.

The single combined interrupt output may be used with a system interrupt controller, which provides another level of masking on a per-peripheral basis. This allows use of modular device drivers which will always know where to find the interrupt source control register bits.

The individual interrupt requests could also be used with a system interrupt controller that provides masking for the outputs of each peripheral. In this way, a global interrupt service routine would be able to read the entire set of sources from one wide register in the system interrupt controller. This is an attractive option where the time to read from the peripheral registers is significant compared to the CPU clock speed in a real-time system.

The peripheral supports both the above methods, since the overhead is small.

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Functional Overview

2.2.8Synchronizing registers and logic

The PrimeCell ACI supports both asynchronous and synchronous operation of the clocks, PCLK and ACICLK. Synchronization of control signals is performed on both directions of data flow, that is from the PCLK to the ACICLK domain and vice versa.

2.2.9Test registers and logic

Additional registers and logic are incorporated for functional block verification and manufacturing test. Test vectors can be applied via the Test Interface Controller (TIC).

The test logic allows generation of a test clock enable signal to propagate test vectors to the input signals of the block, and capture the values on the block outputs. Test registers should not be read or written to during normal use.

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ARM DDI 0146C