Furber S.ARM system-on-chip architecture.2000

The VLSI ISDN Subscriber Processor

349

Figure 13.1 Ruby II advanced communication controller organization.

13.2The VLSI ISDN Subscriber Processor

The VLSI ISDN Subscriber Processor (VIP) is a programmable engine for ISDN (Integrated Services Digital Network; a digital telephony standard) subscriber communications. The design was developed by Hagenuk GmbH for use in their ISDN product range and subsequently licensed back to VLSI Technology for sale as an ASSP (Application Specific Standard Part). It incorporates most of the circuitry required to implement a full-feature ISDN terminal, supporting voice, data and video services down the same digital line. The sort of applications it is targeted at include:

• ISDN terminal equipment, such as domestic and digital PABX telephones, H.320 videophones and integrated PC communications.

350	Embedded ARM Applications

•ISDN to DECT (Digital European Cordless Telephone) controllers, allowing a number of cordless telephones to link to each other and to an ISDN line for domestic and business use.

•ISDN to PCMCIA communication cards.

The VIP chip incorporates the specialized interfaces required to connect to the ISDN SO-interface, support for telephony interfaces such as a numeric keypad, a number display, a microphone and an earphone, digital links for external signal processors or codecs, and power management features such as a programmable clock and an analogue to digital converter to monitor the battery state.

The ARM6 core performs general control and ISDN protocol functions. A 3 Kbyte on-chip RAM operates without wait states at the full processor clock rate of 36.864 MHz. Critical code routines can be loaded into this RAM as required, for example, the signal processing routines required to support hands-free operation.

VIP organization	The organization of the VIP chip is illustrated in Figure 13.2 on page 351 and a
	typical system configuration is shown in Figure 13.3 on page 352.
Memory	The external memory interface supports 8-, 16and 32-bit off-chip static RAMs and
interface	ROMs and 16and 32-bit dynamic RAMs. The addressable memory is divided into
	four ranges, each of which operates with a programmable number of wait states
	(where the minimum is one wait state giving a 54 ns access time).
SO-interface	The on-chip ISDN SO-interface allows connection to an SO-interface bus via isolat-
	ing transformers and surge protection. The on-chip functions include a phase-locked
	loop for data and clock recovery, framing, and low-level protocols. The 192 Kbit/s
	raw data rate includes two 64 Kbit/s B channels and one 16 Kbit/s D channel. In
	telephony applications the B channels carry 8-bit speech samples at an 8 KHz
	sample rate and the D channel is used for control purposes.
Codec	The G.711 codec includes an on-chip analogue front end that allows direct connec-
	tion to both a telephone handset and a hands-free microphone and speaker. The
	input and output channels have independently programmable gains. The amplifica-
	tion stages have power-down modes to save power when they are inactive.
ADCs	The on-chip analogue to digital converters are based upon timing how long it takes
	to discharge a capacitor to the input voltage level. This is a very simple way to
	measure slowly varying voltages, requiring little more than an on-chip comparator,
	an output to charge the capacitor at the start of the conversion and a means of meas-
	uring the time from the start of the conversion to the point where the comparator
	switches. Typical uses would be to measure the voltage from a volume control
	potentiometer or to check the battery voltage in a portable application.

The VLSI ISDN Subscriber Processor

351

Figure 13.2 VIP organization.

Keypad interface The keyboard interface uses parallel output ports to strobe the columns of the keypad and parallel input ports with internal pull-down resistors to sense the rows. An OR gate on the inputs can generate an interrupt. If all the column outputs are active, any key press will generate an interrupt whereupon the ARM can activate individual col-

	umns and sense individual rows to determine the particular key pressed.
Clocks and	The chip has two clock sources. Normal operation is at 38.864 MHz, with 460.8
timers	KHz used during power-down. A watchdog timer resets the CPU if there is no activ-
	ity for 1.28 seconds, and a 2.5 ms tinier interrupts the processor from sleep mode
	for DRAM refresh and multitasking purposes.

352	Embedded ARM Applications

Figure 13.3 Typical VIP system configuration.

13.3The OneC™ VWS22100 GSM chip

	The OneC VWS22100, developed by VLSI Technology, Inc., is a system-on-chip
	design for a GSM mobile telephone handset. With the addition of external program
	and data memory and a suitable radio module it provides all the functions required
	in a handset. An example of a GSM handset that uses the OneC VWS22100 inte-
	grated baseband device is the Samsung SGH2400, a dual-band (GSM 900/1800)
	handset with hands-free voice-activated dialling, shown in Figure 13.4 on page 353.
VWS22100	The system architecture of the OneC VWS22100 is typical of a controller used in
organization	today's mobile phone handsets, incorporating an ARM7TDMI core as a
	general-purpose controller handling the user interface and certain GSM protocol
	layers and a DSP core to handle the baseband signal processing aided by some
	special-purpose signal processing hardware blocks. It is illustrated in Figure 13.5 on
	page 354.
DSP subsystem	The DSP subsystem (shown in the shaded rectangle in Figure 13.5) is based around
	the 16-bit Oak DSP core. It performs all the real-time signal processing functions
	which include:
	•	voice coding;
	•	equalization;

The OneC™ VWS22100 GSM	353
chip

Figure 13.4 Samsung's SGH2400 GSM handset uses the OneC VWS22100.

ARM7TDMI subsystem

Duty allocation

•channel coding;

•echo cancellation;

•noise suppression;

•voice recognition;

•data compression.

The ARM7TDMI core is responsible for the system control functions which include:

•the user interface software;

•the GSM protocol stack;

•power management;

•driving the peripheral interfaces;

•running some data applications.

The split of tasks between the ARM and Oak cores can be illustrated by examining some of the details in Figure 13.5.

354	Embedded ARM Applications

Figure 13.5 OneC VWS22100 GSM chip organization.

The audio and radio interfaces (on the left of the figure) are connected to both processing systems. The ARM system sets the gains of the amplifiers, controlling the radio transmission power level and the frequency synthesizers, causing the ringer to inform the user of an incoming call, and so on.

The Ericsson-VLSI Bluetooth Baseband Controller

355

On-chip debug

Power management

GSM handset

The data streams, which include the encoded voice data and the symbols transmitted and received over the radio link, pass directly between the Oak system and the peripheral interfaces.

There are two heterogeneous processing systems on the chip. The on-chip debug hardware employs a single JTAG interface to access several debug features, including the ARM7TDMI EmbeddedlCE module, debug technology on the Oak DSP core, and other test and debug facilities.

The battery life of a mobile telephone handset is a significant issue in the present market-place; 'talk-time' and 'standby' times feature prominently in product advertising. The OneC VWS22100 incorporates a number of power management features to optimize the performance of the product it controls:

•global and selective power-down modes;

•the ability to slow down the system clock in idle mode;

•the analogue circuits also can operate at reduced power;

•the on-chip pulse-width modulation outputs control battery charging;

•the on-chip analogue-to-digital converters (ADCs) provide for the monitoring of the temperature and battery voltage to give optimum operation.

The typical hardware architecture of a GSM cellular telephone handset based around the OneC VWS22100 is illustrated in Figure 13.6 on page 356.

13.4The Ericsson-VLSI Bluetooth Baseband Controller

Bluetooth is a de-facto standard for wireless data communication for the 2.4 GHz band developed by a consortium of companies including Ericsson, IBM, Intel, Nokia and Toshiba. The standard is intended to support short-range communication (from 10cm to 10m range) in a manner similar to that currently achieved with infrared communication using the IrDA standard, but avoiding the line-of-sight, alignment, and mutual interference restrictions of IrDA. Using radio communication, Bluetooth is intended to support laptop to cellular telephone, printer, PDA, desktop, fax machines, keyboards, and so on, and it can also provide a bridge to existing data networks. As such it serves as a cable replacement technology for personal networks.

The standard supports a gross data rate of 1 Mbit/s, and uses a frequency hopping scheme and forward error correction to give robust communication in a noisy and uncoordinated environment.

356	Embedded ARM Applications

	Figure 13.6 Typical GSM handset architecture.
	The Ericsson-VLSI Bluetooth Baseband Controller chip is a jointly developed stand-
	ard part which is intended for use in portable Bluetooth-based communication devices.
Bluetooth	Bluetooth units dynamically form ad hoc 'piconets', which are groups of two to
'piconet'	eight units that operate the same frequency-hopping scheme. All of the units are
	equal peers with identical implementations, though one of the units will operate as
	master when the piconet is established. The master defines the clock and hopping
	sequence that synchronize the piconet.
	Multiple piconets can be linked to form a 'scatternet'.
Bluetooth	The organization of the Bluetooth Baseband Controller is illustrated in Figure 13.7 on
controller	page 357. The chip is based around a synthesized ARM7TDMI core and includes 64
organization	Kbytes of fast (zero wait state) on-chip SRAM and a 4K byte instruction cache. Critical
	routines can be loaded into the RAM to get the best performance. The cache improves
	the performance and power-efficiency of code resident in the off-chip memory.
	There is a set of peripheral modules which share a number of pins, including three
	UARTs, a USB interface and an I2C-bus interface. FIFO buffers decouple the proces-
	sor from having to respond to every byte which is transferred through these interfaces.
	The external bus interface supports devices with 8- and 16-bit databuses and has
	flexible wait state generation. The counter timer block has three 8-bit counters con-

The Ericsson-VLSI Bluetooth Baseband Controller

357

	Figure 13.7	Ericsson-VLSI Bluetooth Baseband Controller organization.
	nected to a 24-bit prescaler, and an interrupt controller gives control of all onand
	off-chip interrupt sources.
Ericsson	The Bluetooth Baseband Controller includes a power-optimized hardware block, the
Bluetooth Core	Ericsson Bluetooth Core (EBC), which handles all the Link Controller functionality
	within the Bluetooth specification and includes the interface logic to a Bluetooth

radio implementation. The EBC performs all the packet-handling functions for point-to-point, multislot and point-to-multipoint communications.

The baseband protocol uses a combination of circuit and packet switching. Slots can be reserved for synchronous channels, for example to support voice transmission.

358

Power management

Bluetooth system

Embedded ARM Applications

The chip has four power management modes:

1.On-line: all blocks are clocked at their normal speed. The ARM7TDMI core clock is between 13 and 40 MHz, depending on the application. At the maximum data transfer rate the current consumption is around 30 mA.

2.Command: The ARM7TDMI clock is slowed by the insertion of wait states.

3.Sleep: The ARM7TDMI clock is stopped, as are the clocks to a programmable subset of the other blocks. The current drawn in this mode is around 0.3 mA.

4.Stopped: The clock oscillator is turned off.

A typical Bluetooth system is illustrated in Figure 13.8. The baseband controller chip requires an external radio module and program ROM to complete the system. The high level of integration leads to a very compact and economic implementation of a sophisticated and highly functional radio communication system.

V

Figure 13.8 Typical Bluetooth application.

Bluetooth silicon A photograph of a Bluetooth die is shown in Figure 13.9 on page 359. The die area is dominated by the 64 Kbyte SRAM, with the synthesized EBC (in the bottom right-hand quadrant) being the second largest block.

The synthesized ARM7TDMI core in the top-right corner of the chip has far less visible structure than the ARM7TDMI hard macrocell shown Figure 9.4 on page 255. This is because the hard macrocell was laid out by hand and manual designers use very regular datapath structures to give dense layout and to minimize the number of different cells that must be created. Synthesized cells use less dense and less regular structures. The advantage of the synthesized core is that it can be ported to a new CMOS process much more rapidly.

The characteristics of the Bluetooth core are summarized in Table 13.1 on page 359. The processor is capable of operating at up to 39 MHz, but the data shown in the table are representative of a typical GSM application. The chip I/Os operate at 3.3 V, but the core logic typically operates at 2.5 V