1 Technical task

Which student has individual task. Below the examples of technical task are shown.

Example 1:

Technical task

for the student of the KIA-11 group: _Kolesnik Alina_______________.

Date of fulfilment of the Course Project : 2012, December, 10.

Initial date: 2012, September, 10.

Variant: 23

Virtual Computer ___VC1_____.

Set of instructions: 0-3, 11-14, 5,8

TASK:

1. Describe the Virtual Computer.

2. Write down 3 programs in code of Virtual Computer:

linear program

y = a + b*c - d;

branch

a + b*c – d, if a+b >0

y = a*c – d*b , if a+b =0

(a – b)*c , if a+b <0

loop

y = sum (a[0],a[1] …a[10]).

3. Develop the simulation program:

• realization of the graphics user interface;

• creation and displaying of the memory contents;

• step-by-step execution of program;

• visualization of the state of VC during the program execution.

4. Develop the program documentation:

• user guide;

• program definition;

• test methodic.

5. Prepare the Explanatory Note to the Course Project.

Student ___________ / __________ /

Prof. ___________ /Malcheva R.V./

2 Analyses of virtual computer

Virtual Computer is a simple model of General-purpose digital computer. Computer can follow a sequence of instruction, called a program, which operates on given data. All information in computer is represented in binary form. Both program and data are stored in memory. The control unit in the CPU retrieves the instructions, one by one, from the program stored in the memory unit. When data processing takes place, information from the memory is first transferred to selector registers in the control-processing unit. Intermediate and final results, obtained in the central processing unit, are transferred back to memory.

2.1 General architecture

Computer architecture = structure of hardware + internal language.

Simplest hardware consists of the next units:

• ALU (arithmetical – logical unit);

• CU (control unit);

• RAM (random access memory or memory unit).

A memory unit is a set of binary cells, which is capable of storing a large quantity of binary information. The memory unit is specified by the number of words, it contains, and the number of bits in each word. Examples of VC-structure are shown in fig.1 - fig.3.

Internal computer language includes:

1) O₁, O₂, … O_k - operations;

2) D₁, D₂, …D_l - data formats;

3) A₁, A₂, …A_m – addressing modes;

4) I₁, I₂, …I_n – instructions formats.

I = O + D + A

Virtual computers use only fixed point notation – integer numbers. Examples of instructions’ sets are shown in tabl.1 (VC1), tabl.2 (VC2).

Table 1 - Instruction System of VC1

Operation		Name of instruction	Indications				Instruction’s execution
COP	Assemb		S	Z	C	E
0000	NOP	No operation	–	–	–	–
0001	STOP	Stop	–	–	–	–
0010	LOAD	Loading	–	–	–	–	(Aex) AC*
0011	SAVE	Writing	–	–	–	–	(AC) Aex
0100	NOT	Negation	+	+	–	–	()AC
0101	OR	Disjunction	+	+	–	–
0110	AND	Conjunction	+	+	–	–
0111	ADD	Addition	+	+	+	–	(AC)(Aex) AC
1000	MUL	Multiplication	+	+	+	–
1001	DIV	Division	+	+	+	–
1010	MOD2	Modulo 2 sum	+	+	–	–
1011	JS	Conditional jump by S	–	–	–	–	AexSAK, if S = 1
1100	JZ	Conditional jump by Z	–	–	–	–	AexSAK, if Z = 1
1101	JMP	Unconditional jump	–	–	–	–	AexSAK
1110	INC	Increment of location	–	–	–	+	1) (Aex )+1Aex 2) (Aex) = 0 => ignoring next command
1111	CALL	Subroutine call	–	–	–	–	See remark **

Remarks:

*as accumulator one of the registers R0, R1, R2 or R3 is used depending on the indication of the field NR of the RI.

** During subroutine call return address is stored in the first location of the subroutine. That is why the subroutine must begin from the 2 instruction “no operation”. Control transfer is realized by A_ex.

Address A_ex. equal AM, if MA=0,

(AM), if MA=1.

Table 2 - Instruction System of VC2

Operation		Name of instruction	Indications				Instruction’s execution
COP	Assemb		S	Z	C	E
0000	NOP	No operation	–	–	–	–
0001	STOP	Stop	–	–	–	–
0010	LOAD	Loading	–	–	–	–	(Aex) AC*
0011	SAVE	Writing	–	–	–	–	(AC) Aex
0100	NOT	Negation	+	+	–	–	()AC
0101	OR	Disjunction	+	+	–	–
0110	AND	Conjunction	+	+	–	–
0111	ADD	Addition	+	+	+	–	(AC)(Aex) AC
1000	MUL	Multiplication	+	+	+	–
1001	DIV	Division	+	+	+	–
1010	MOD2	Modulo 2 sum	+	+	–	–
1011	JS	Conditional jump by S	–	–	–	–	AexSAK, if S = 1
1100	JZ	Conditional jump by Z	–	–	–	–	AexSAK, if Z = 1
1101	JMP	Unconditional jump	–	–	–	–	AexSAK
1110	INC	Increment of location	–	–	–	+	1) (Aex )+1Aex 2) (Aex) = 0 => ignoring next command
1111	CALL	Subroutine call	–	–	–	–	See remark **

Remarks:

*as accumulator registers 0P1 (for loading) and RES (for storing) are used

** During subroutine call return address is stored in the first location of the subroutine. That is why the subroutine must begin from the 2 instruction “no operation”. Control transfer is realized by A_ex.

Address A_ex. equal AM, if MA=0,

(AM), if MA=1.

Definition of VC3.

Virtual computer VC3 is a 8^th –bits Computer. It uses 8^th –bit Registers, Operands and Addresses. Only Instructions are allocated 16 bits (2 memory words). To store instruction VC uses a standard way: at first low byte (bits 7…0) is stored to memory word, then, to the next word the high byte (bits 15…8) is stored.

Instruction register (IR) has the next structure:

COP – code of operation (000, 001 … 111);

AM – addressing mode (00, 01, 10, 11);

NR – number of register (000, 001 … 111);

AMW – address of memory word, number of register or 8^th-bits immediate data.

Table 3 - Instruction System of VC3

Operation		Name of instruction	Flags			Explanation
COP	Assemb		S	Z	C
000	STOP	Stop	–	–	–
001	LOAD	Loading	–	–	–	(Aex) Rn*
010	SAVE	Writing	–	–	–	(Rn) Aex
011	**	**	+	+	+
100	**	**	+	+	+	(Rn)(Aex) Rn
101	**	**	+	+	+
110	J?**	Conditional jump **	–	–	–	AexPC, if <condition> is TRUE
111	JMP	Unconditional jump	–	–	–	AexPC

Remarks:

*as Rn one of the registers AL, AH, BL, BH, CL, CH, DL or DH is used depending on the indication of the field NR of the IR.

** - see individual variant.

Address of memory word, A_ex, depends on addressing mode, AM.

A_ex =AMW, if AM=00 – direct addressing mode;

A_ex =(AMW), if AM=01 – indirect addressing mode;

if AM=10, bits [2…0] of AMW show number of register (bits [7…3] have to be equal to 0)– register direct addressing mode;

if AM=11, AMW consists constant data – immediate addressing mode.

The structures and instructions’ sets for all VC are in Appendix C.