Functional Overview

Note

The minimum HIGH phase duration supported is limited to 2/16 of the carrier period and a value 0000 is an invalid selection.

2.4.8Clock dividers

The reference clock input GIRCLK is used to drive programmable dividers within the block, which generate the internal clock frequencies used by the transmit and receive logic. The internal clock frequency must be 16 times the carrier frequency when modulation, or demodulation is in use. If a carrier is not required, the clock rate selected does not have to be 16 times the symbol rate (though often it will be). A separate divider is provided for transmit and receive paths. The registers GIRRXGENCR and GIRTXGENCR need to be programmed with the value clkdiv for the receive and transmit clock dividers respectively.

When carrier modulation and demodulation is required in the receive or transmit logic, the required divisor to create the correct internal clock is given by:

Divisor = FGIR / (16 x carrier rate)

where FGIR is the input clock frequency of GIRCLK.

When no demodulation or modulation is required, the internal frequency can be set by the incoming symbol rate (the repetition rate of the HIGHs and LOWs on the data). Assuming the use of 16 times the symbol rate, the required divisor to create the correct internal clock is given by:

Divisor = FGIR / (16 x symbol rate)

where FGIR is the PrimeCell GIR input reference clock frequency.

The value written to the clock generator control register GIRRXGENCR and

GIRTXGENCR is related to the divisor as stated below:

clkdiv = Divisor – 1.

2-16

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ARM DDI 0149B