- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Further reading
- •ARM publications
- •Feedback
- •Feedback on this document
- •Feedback on the ARM PrimeCell Generic Infrared Interface (PL140)
- •Introduction
- •1.1 About the ARM PrimeCell Generic Infrared Interface (PL140)
- •1.1.1 Features of the PrimeCell GIR
- •1.1.2 Programmable parameters
- •1.2 Block diagram
- •1.3 AMBA compatibility
- •Functional Overview
- •2.1 ARM PrimeCell Generic Infrared Interface (PL140) overview
- •2.2 PrimeCell GIR functional description
- •2.2.1 AMBA APB interface
- •2.2.2 Register block
- •2.2.3 Receive and transmit clock divider
- •2.2.4 Transmit FIFO
- •2.2.5 Receive FIFO
- •2.2.6 Transmit logic
- •2.2.7 Receive logic
- •2.2.8 Interrupt generation logic
- •2.2.9 Synchronizing registers and logic
- •2.2.10 Test registers and logic
- •2.3 Infrared methodology
- •2.4 PrimeCell GIR operation
- •2.4.1 Interface reset
- •2.4.2 Clock signals
- •2.4.3 Receive processing
- •2.4.4 Receive demodulation
- •2.4.5 Receive FIFO information
- •2.4.6 Transmit processing
- •2.4.7 Transmit modulation
- •2.4.8 Clock dividers
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Summary of PrimeCell GIR registers
- •3.3 Register descriptions
- •3.3.1 GIRFCR: [15] (+ 0x00)
- •3.3.5 GIRSTAT: [8] (+0x10)
- •3.3.7 GIRIIR/GIRICR: [3/0] (+0x18)
- •Programmer’s Model for Test
- •4.1 PrimeCell GIR test harness overview
- •4.2 Scan testing
- •4.3 Test registers
- •4.3.4 GIRTISR: [1] (+0x88)
- •4.3.5 GIRTOCR: [5] (+0x8c)
- •4.3.6 GIRTTXCDC [16] (+0x90)
- •4.3.7 GIRTRXCDC [16] (+0x94)
- •4.3.8 GIRTTXC [20] (+0x98)
- •4.3.9 GIRTRXPTC [20] (+0x9c)
- •4.3.10 GIRTDC [7] (+0xa0)
- •A.1 AMBA APB signals
- •A.2 On-chip signals
- •A.3 Signals to pads
Chapter 2
Functional Overview
This chapter describes the major functional blocks of the ARM PrimeCell Generic Infrared Interface (PL140):
•ARM PrimeCell Generic Infrared Interface (PL140) overview on page 2-2
•PrimeCell GIR functional description on page 2-3
•PrimeCell GIR operation on page 2-11.
ARM DDI 0149B |
© Copyright ARM Limited 1999. All rights reserved. |
2-1 |
Functional Overview
2.1ARM PrimeCell Generic Infrared Interface (PL140) overview
The PrimeCell GIR can be used to implement a generic infrared interface, which can communicate using most of the commonly available standards, to an infrared peripheral device such as a remote control. This flexibility has been achieved using programmable features in the PrimeCell GIR, and implementing the various data encoding/decoding protocols in software.
The CPU reads and writes data and control/status information via the AMBA APB interface. The transmit and receive paths are buffered with internal FIFO memories allowing up to sixteen 17-bit values to be stored independently in both transmit and receive modes. Serial data are transmitted on GIROUT and received on GIRIN.
Data are encoded/decoded in software and then communicated as a serial stream of digital binary symbols which may or may not be modulated on a relatively high frequency carrier signal (20-60kHz).
Received pulse width values are stored in the receive FIFO, and transmit pulse widths are generated according to the values read from the transmit FIFO.
The PrimeCell GIR includes independent transmit and receive programmable clock generation. It divides down the input reference clock GIRCLK, to generate the internal clock enable frequencies used by the transmit and receive logic.
Modulation and demodulation can be enabled or disabled according to whether data are modulated on a carrier, or data are sent using direct pulse transmission. The input reference clock GIRCLK, should be sixteen times the modulation carrier frequency
and the duty cycle of the transmitted carrier pulses is programmable from 1/16 to 15/16 of the carrier signal period using GIRTXDUTYCR.
The PrimeCell GIR operating modes are programmed using the function control register GIRFCR.
Three individually maskable interrupt outputs are generated:
•GIRTXINTR requests servicing of the transmit buffer
•GIRRXINTR requests servicing of the receive buffer
•GIRRORINTR indicates an overrun condition in the receive FIFO.
A single combined interrupt, GIRINTR output is asserted if any of the individual interrupts are asserted and unmasked.
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© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0149B |